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review.coreboot.org / coreboot / 9631016660423d0585a1 / . / src / cpu / x86 / 32bit / entry32.inc
blob: 9ef3bc1c6e8302b0f2d98949c6adba2cf9f0cd80 [file] [log] [blame]
Stefan Reinauerf8ee1802008-01-18 15:08:58 +0000[diff] [blame]1/* For starting coreboot in protected mode */
Eric Biedermanfcd5ace2004-10-14 19:29:29 +0000[diff] [blame]2
3#include <arch/rom_segs.h>
Alexandru Gagniuc5005bb062011-04-11 20:17:22 +0000[diff] [blame]4#include <cpu/x86/post_code.h>
Eric Biedermanfcd5ace2004-10-14 19:29:29 +0000[diff] [blame]5
Eric Biedermanfcd5ace2004-10-14 19:29:29 +0000[diff] [blame]6 .code32
7
Stefan Reinauera6f0e122010-08-14 17:27:27 +0000[diff] [blame]8
Patrick Georgi472efa62012-02-16 20:44:20 +0100[diff] [blame]9 /* This is the GDT for the ROM stage part of coreboot. It
10 * is different from the RAM stage GDT which is defined in
Stefan Reinauera6f0e122010-08-14 17:27:27 +0000[diff] [blame]11 * c_start.S
12 */
13
Eric Biedermanfcd5ace2004-10-14 19:29:29 +0000[diff] [blame]14 .align 4
15.globl gdtptr
Eric Biedermanfcd5ace2004-10-14 19:29:29 +0000[diff] [blame]16gdt:
17gdtptr:
18 .word gdt_end - gdt -1 /* compute the table limit */
19 .long gdt /* we know the offset */
20 .word 0
21
Li-Ta Lof84926e2004-11-04 18:36:06 +0000[diff] [blame]22 /* selgdt 0x08, flat code segment */
Stefan Reinauer14e22772010-04-27 06:56:47 +0000[diff] [blame]23 .word 0xffff, 0x0000
24 .byte 0x00, 0x9b, 0xcf, 0x00 /* G=1 and 0x0f, So we get 4Gbytes for limit */
Li-Ta Lof84926e2004-11-04 18:36:06 +0000[diff] [blame]25
26 /* selgdt 0x10,flat data segment */
Stefan Reinauer14e22772010-04-27 06:56:47 +0000[diff] [blame]27 .word 0xffff, 0x0000
Yinghai Lu21332b82007-04-06 19:49:05 +0000[diff] [blame]28 .byte 0x00, 0x93, 0xcf, 0x00
Eric Biedermanfcd5ace2004-10-14 19:29:29 +0000[diff] [blame]29
Stefan Reinauere021dea2015-06-18 01:15:27 -0700[diff] [blame]30 /* selgdt 0x18, flat code segment (64-bit) */
31 .word 0xffff, 0x0000
32 .byte 0x00, 0x9b, 0xaf, 0x00
33
Eric Biedermanfcd5ace2004-10-14 19:29:29 +0000[diff] [blame]34gdt_end:
Stefan Reinauer14e22772010-04-27 06:56:47 +0000[diff] [blame]35
Eric Biedermanfcd5ace2004-10-14 19:29:29 +0000[diff] [blame]36
37/*
Stefan Reinauer14e22772010-04-27 06:56:47 +0000[diff] [blame]38 * When we come here we are in protected mode. We expand
Eric Biedermanfcd5ace2004-10-14 19:29:29 +0000[diff] [blame]39 * the stack and copies the data segment from ROM to the
40 * memory.
41 *
42 * After that, we call the chipset bootstrap routine that
Stefan Reinauer14e22772010-04-27 06:56:47 +0000[diff] [blame]43 * does what is left of the chipset initialization.
Eric Biedermanfcd5ace2004-10-14 19:29:29 +0000[diff] [blame]44 *
45 * NOTE aligned to 4 so that we are sure that the prefetch
46 * cache will be reloaded.
47 */
48 .align 4
49.globl protected_start
50protected_start:
51
52 lgdt %cs:gdtptr
53 ljmp $ROM_CODE_SEG, $__protected_start
Stefan Reinauer14e22772010-04-27 06:56:47 +0000[diff] [blame]54
Eric Biedermanfcd5ace2004-10-14 19:29:29 +0000[diff] [blame]55__protected_start:
56 /* Save the BIST value */
57 movl %eax, %ebp
58
Martin Roth14554372015-11-12 14:02:42 -0700[diff] [blame]59#if !IS_ENABLED(CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES)
Alexandru Gagniuc5005bb062011-04-11 20:17:22 +0000[diff] [blame]60 post_code(POST_ENTER_PROTECTED_MODE)
Martin Roth14554372015-11-12 14:02:42 -0700[diff] [blame]61#endif
Eric Biedermanfcd5ace2004-10-14 19:29:29 +0000[diff] [blame]62
63 movw $ROM_DATA_SEG, %ax
64 movw %ax, %ds
65 movw %ax, %es
66 movw %ax, %ss
67 movw %ax, %fs
68 movw %ax, %gs
69
70 /* Restore the BIST value to %eax */
71 movl %ebp, %eax