Stefan Reinauer | c7757f2 | 2009-04-30 10:14:22 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 3 | * |
Stefan Reinauer | c7757f2 | 2009-04-30 10:14:22 +0000 | [diff] [blame] | 4 | * Copyright (C) 2007-2009 coresystems GmbH |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License as |
| 8 | * published by the Free Software Foundation; version 2 of |
| 9 | * the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Stefan Reinauer | c7757f2 | 2009-04-30 10:14:22 +0000 | [diff] [blame] | 15 | */ |
| 16 | |
Stefan Reinauer | 00a889c | 2008-10-29 04:48:44 +0000 | [diff] [blame] | 17 | #include <console/console.h> |
| 18 | #include <device/device.h> |
Stefan Reinauer | 00a889c | 2008-10-29 04:48:44 +0000 | [diff] [blame] | 19 | #include <string.h> |
| 20 | #include <cpu/cpu.h> |
| 21 | #include <cpu/x86/mtrr.h> |
| 22 | #include <cpu/x86/msr.h> |
| 23 | #include <cpu/x86/lapic.h> |
| 24 | #include <cpu/intel/microcode.h> |
Stefan Reinauer | 2a27b20 | 2010-12-11 22:14:44 +0000 | [diff] [blame] | 25 | #include <cpu/intel/speedstep.h> |
Stefan Reinauer | 00a889c | 2008-10-29 04:48:44 +0000 | [diff] [blame] | 26 | #include <cpu/intel/hyperthreading.h> |
| 27 | #include <cpu/x86/cache.h> |
Uwe Hermann | aac8f66 | 2010-09-29 09:54:16 +0000 | [diff] [blame] | 28 | #include <cpu/x86/name.h> |
Stefan Reinauer | 00a889c | 2008-10-29 04:48:44 +0000 | [diff] [blame] | 29 | |
Stefan Reinauer | 45cc550 | 2009-03-06 19:54:15 +0000 | [diff] [blame] | 30 | #define IA32_FEATURE_CONTROL 0x003a |
| 31 | |
| 32 | #define CPUID_VMX (1 << 5) |
| 33 | #define CPUID_SMX (1 << 6) |
| 34 | static void enable_vmx(void) |
| 35 | { |
| 36 | struct cpuid_result regs; |
| 37 | msr_t msr; |
| 38 | |
| 39 | msr = rdmsr(IA32_FEATURE_CONTROL); |
| 40 | |
| 41 | if (msr.lo & (1 << 0)) { |
| 42 | /* VMX locked. If we set it again we get an illegal |
| 43 | * instruction |
| 44 | */ |
| 45 | return; |
| 46 | } |
| 47 | |
| 48 | regs = cpuid(1); |
| 49 | if (regs.ecx & CPUID_VMX) { |
| 50 | msr.lo |= (1 << 2); |
| 51 | if (regs.ecx & CPUID_SMX) |
| 52 | msr.lo |= (1 << 1); |
| 53 | } |
| 54 | |
| 55 | wrmsr(IA32_FEATURE_CONTROL, msr); |
| 56 | |
| 57 | msr.lo |= (1 << 0); /* Set lock bit */ |
| 58 | |
| 59 | wrmsr(IA32_FEATURE_CONTROL, msr); |
| 60 | } |
| 61 | |
Stefan Reinauer | 4da810b | 2009-07-21 21:41:42 +0000 | [diff] [blame] | 62 | #define HIGHEST_CLEVEL 3 |
Stefan Reinauer | 45cc550 | 2009-03-06 19:54:15 +0000 | [diff] [blame] | 63 | static void configure_c_states(void) |
| 64 | { |
| 65 | msr_t msr; |
| 66 | |
Patrick Georgi | 644e83b | 2013-02-09 15:35:30 +0100 | [diff] [blame] | 67 | msr = rdmsr(MSR_PMG_CST_CONFIG_CONTROL); |
Stefan Reinauer | 45cc550 | 2009-03-06 19:54:15 +0000 | [diff] [blame] | 68 | |
| 69 | msr.lo |= (1 << 15); // config lock until next reset |
| 70 | msr.lo |= (1 << 14); // Deeper Sleep |
| 71 | msr.lo |= (1 << 10); // Enable IO MWAIT redirection |
| 72 | msr.lo &= ~(1 << 9); // Issue a single stop grant cycle upon stpclk |
| 73 | msr.lo |= (1 << 3); // Dynamic L2 |
| 74 | |
Stefan Reinauer | 4da810b | 2009-07-21 21:41:42 +0000 | [diff] [blame] | 75 | /* Number of supported C-States */ |
| 76 | msr.lo &= ~7; |
| 77 | msr.lo |= HIGHEST_CLEVEL; // support at most C3 |
| 78 | |
Patrick Georgi | 644e83b | 2013-02-09 15:35:30 +0100 | [diff] [blame] | 79 | wrmsr(MSR_PMG_CST_CONFIG_CONTROL, msr); |
Stefan Reinauer | 45cc550 | 2009-03-06 19:54:15 +0000 | [diff] [blame] | 80 | |
| 81 | /* Set Processor MWAIT IO BASE */ |
| 82 | msr.hi = 0; |
| 83 | msr.lo = ((PMB0_BASE + 4) & 0xffff) | (((PMB1_BASE + 9) & 0xffff) << 16); |
Patrick Georgi | 644e83b | 2013-02-09 15:35:30 +0100 | [diff] [blame] | 84 | wrmsr(MSR_PMG_IO_BASE_ADDR, msr); |
Stefan Reinauer | 45cc550 | 2009-03-06 19:54:15 +0000 | [diff] [blame] | 85 | |
Stefan Reinauer | 4da810b | 2009-07-21 21:41:42 +0000 | [diff] [blame] | 86 | /* Set C_LVL controls and IO Capture Address */ |
Stefan Reinauer | 45cc550 | 2009-03-06 19:54:15 +0000 | [diff] [blame] | 87 | msr.hi = 0; |
Stefan Reinauer | 4da810b | 2009-07-21 21:41:42 +0000 | [diff] [blame] | 88 | msr.lo = (PMB0_BASE + 4) | ((HIGHEST_CLEVEL - 2) << 16); // -2 because LVL0+1 aren't counted |
Patrick Georgi | 644e83b | 2013-02-09 15:35:30 +0100 | [diff] [blame] | 89 | wrmsr(MSR_PMG_IO_CAPTURE_ADDR, msr); |
Stefan Reinauer | 45cc550 | 2009-03-06 19:54:15 +0000 | [diff] [blame] | 90 | } |
| 91 | |
| 92 | #define IA32_MISC_ENABLE 0x1a0 |
Sven Schnelle | edac28c | 2012-06-19 18:00:01 +0200 | [diff] [blame] | 93 | #define IA32_PECI_CTL 0x5a0 |
| 94 | |
Stefan Reinauer | 45cc550 | 2009-03-06 19:54:15 +0000 | [diff] [blame] | 95 | static void configure_misc(void) |
| 96 | { |
| 97 | msr_t msr; |
| 98 | |
| 99 | msr = rdmsr(IA32_MISC_ENABLE); |
| 100 | msr.lo |= (1 << 3); /* TM1 enable */ |
| 101 | msr.lo |= (1 << 13); /* TM2 enable */ |
| 102 | msr.lo |= (1 << 17); /* Bidirectional PROCHOT# */ |
| 103 | |
| 104 | msr.lo |= (1 << 10); /* FERR# multiplexing */ |
| 105 | |
| 106 | // TODO: Only if IA32_PLATFORM_ID[17] = 0 and IA32_PLATFORM_ID[50] = 1 |
| 107 | msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */ |
| 108 | |
| 109 | /* Enable C2E */ |
| 110 | msr.lo |= (1 << 26); |
| 111 | |
| 112 | /* Enable C4E */ |
| 113 | /* TODO This should only be done on mobile CPUs, see cpuid 5 */ |
| 114 | msr.hi |= (1 << (32 - 32)); // C4E |
| 115 | msr.hi |= (1 << (33 - 32)); // Hard C4E |
| 116 | |
| 117 | /* Enable EMTTM. */ |
| 118 | /* NOTE: We leave the EMTTM_CR_TABLE0-5 at their default values */ |
| 119 | msr.hi |= (1 << (36 - 32)); |
| 120 | |
| 121 | wrmsr(IA32_MISC_ENABLE, msr); |
| 122 | |
| 123 | msr.lo |= (1 << 20); /* Lock Enhanced SpeedStep Enable */ |
| 124 | wrmsr(IA32_MISC_ENABLE, msr); |
Patrick Georgi | ac624a6 | 2011-08-09 08:52:14 +0200 | [diff] [blame] | 125 | |
| 126 | // set maximum CPU speed |
| 127 | msr = rdmsr(IA32_PERF_STS); |
| 128 | int busratio_max=(msr.hi >> (40-32)) & 0x1f; |
| 129 | |
| 130 | msr = rdmsr(IA32_PLATFORM_ID); |
| 131 | int vid_max=msr.lo & 0x3f; |
| 132 | |
| 133 | msr.lo &= ~0xffff; |
| 134 | msr.lo |= busratio_max << 8; |
| 135 | msr.lo |= vid_max; |
| 136 | |
| 137 | wrmsr(IA32_PERF_CTL, msr); |
Sven Schnelle | edac28c | 2012-06-19 18:00:01 +0200 | [diff] [blame] | 138 | |
| 139 | /* Enable PECI */ |
| 140 | msr = rdmsr(IA32_PECI_CTL); |
| 141 | msr.lo |= 1; |
| 142 | wrmsr(IA32_PECI_CTL, msr); |
| 143 | |
Stefan Reinauer | 45cc550 | 2009-03-06 19:54:15 +0000 | [diff] [blame] | 144 | } |
| 145 | |
| 146 | #define PIC_SENS_CFG 0x1aa |
| 147 | static void configure_pic_thermal_sensors(void) |
| 148 | { |
| 149 | msr_t msr; |
| 150 | |
| 151 | msr = rdmsr(PIC_SENS_CFG); |
| 152 | |
| 153 | msr.lo |= (1 << 21); // inter-core lock TM1 |
| 154 | msr.lo |= (1 << 4); // Enable bypass filter |
| 155 | |
| 156 | wrmsr(PIC_SENS_CFG, msr); |
| 157 | } |
| 158 | |
Edward O'Callaghan | 2c9d2cf | 2014-10-27 23:29:29 +1100 | [diff] [blame] | 159 | static void model_6fx_init(struct device *cpu) |
Stefan Reinauer | 00a889c | 2008-10-29 04:48:44 +0000 | [diff] [blame] | 160 | { |
| 161 | char processor_name[49]; |
| 162 | |
| 163 | /* Turn on caching if we haven't already */ |
| 164 | x86_enable_cache(); |
| 165 | |
| 166 | /* Update the microcode */ |
Alexandru Gagniuc | 2c38f50 | 2013-12-06 23:14:54 -0600 | [diff] [blame] | 167 | intel_update_microcode_from_cbfs(); |
Stefan Reinauer | 00a889c | 2008-10-29 04:48:44 +0000 | [diff] [blame] | 168 | |
| 169 | /* Print processor name */ |
| 170 | fill_processor_name(processor_name); |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 171 | printk(BIOS_INFO, "CPU: %s.\n", processor_name); |
Stefan Reinauer | 00a889c | 2008-10-29 04:48:44 +0000 | [diff] [blame] | 172 | |
| 173 | /* Setup MTRRs */ |
Sven Schnelle | adfbcb79 | 2012-01-10 12:01:43 +0100 | [diff] [blame] | 174 | x86_setup_mtrrs(); |
Stefan Reinauer | 00a889c | 2008-10-29 04:48:44 +0000 | [diff] [blame] | 175 | x86_mtrr_check(); |
Stefan Reinauer | 45cc550 | 2009-03-06 19:54:15 +0000 | [diff] [blame] | 176 | |
Stefan Reinauer | 4da810b | 2009-07-21 21:41:42 +0000 | [diff] [blame] | 177 | /* Setup Page Attribute Tables (PAT) */ |
| 178 | // TODO set up PAT |
| 179 | |
Stefan Reinauer | 00a889c | 2008-10-29 04:48:44 +0000 | [diff] [blame] | 180 | /* Enable the local cpu apics */ |
| 181 | setup_lapic(); |
| 182 | |
Stefan Reinauer | 45cc550 | 2009-03-06 19:54:15 +0000 | [diff] [blame] | 183 | /* Enable virtualization */ |
| 184 | enable_vmx(); |
| 185 | |
| 186 | /* Configure C States */ |
| 187 | configure_c_states(); |
| 188 | |
| 189 | /* Configure Enhanced SpeedStep and Thermal Sensors */ |
| 190 | configure_misc(); |
| 191 | |
| 192 | /* PIC thermal sensor control */ |
| 193 | configure_pic_thermal_sensors(); |
Sven Schnelle | 51676b1 | 2012-07-29 19:18:03 +0200 | [diff] [blame] | 194 | |
| 195 | /* Start up my cpu siblings */ |
| 196 | intel_sibling_init(cpu); |
Stefan Reinauer | 00a889c | 2008-10-29 04:48:44 +0000 | [diff] [blame] | 197 | } |
| 198 | |
| 199 | static struct device_operations cpu_dev_ops = { |
Stefan Reinauer | 45cc550 | 2009-03-06 19:54:15 +0000 | [diff] [blame] | 200 | .init = model_6fx_init, |
Stefan Reinauer | 00a889c | 2008-10-29 04:48:44 +0000 | [diff] [blame] | 201 | }; |
| 202 | |
| 203 | static struct cpu_device_id cpu_table[] = { |
| 204 | { X86_VENDOR_INTEL, 0x06f0 }, /* Intel Core 2 Solo/Core Duo */ |
Stefan Reinauer | c7757f2 | 2009-04-30 10:14:22 +0000 | [diff] [blame] | 205 | { X86_VENDOR_INTEL, 0x06f2 }, /* Intel Core 2 Solo/Core Duo */ |
Stefan Reinauer | 00a889c | 2008-10-29 04:48:44 +0000 | [diff] [blame] | 206 | { X86_VENDOR_INTEL, 0x06f6 }, /* Intel Core 2 Solo/Core Duo */ |
Stefan Reinauer | c7757f2 | 2009-04-30 10:14:22 +0000 | [diff] [blame] | 207 | { X86_VENDOR_INTEL, 0x06f7 }, /* Intel Core 2 Solo/Core Duo */ |
| 208 | { X86_VENDOR_INTEL, 0x06fa }, /* Intel Core 2 Solo/Core Duo */ |
| 209 | { X86_VENDOR_INTEL, 0x06fb }, /* Intel Core 2 Solo/Core Duo */ |
| 210 | { X86_VENDOR_INTEL, 0x06fd }, /* Intel Core 2 Solo/Core Duo */ |
Peter Stuge | 4c5786b | 2009-10-01 22:34:18 +0000 | [diff] [blame] | 211 | { X86_VENDOR_INTEL, 0x10676 }, /* Core2 Duo E8200 */ |
Stefan Reinauer | 00a889c | 2008-10-29 04:48:44 +0000 | [diff] [blame] | 212 | { 0, 0 }, |
| 213 | }; |
| 214 | |
| 215 | static const struct cpu_driver driver __cpu_driver = { |
| 216 | .ops = &cpu_dev_ops, |
| 217 | .id_table = cpu_table, |
| 218 | }; |