blob: 3adee6f34fbec98aac7e8f5de04ffd2a1a1855e0 [file] [log] [blame]
Joseph Smith40bffc22010-06-21 19:40:09 +00001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2007-2009 coresystems GmbH
5 * Copyright (C) 2010 Joseph Smith <joe@settoplinux.org>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; version 2 of
10 * the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
Joseph Smith40bffc22010-06-21 19:40:09 +000016 */
17
18#include <console/console.h>
19#include <device/device.h>
Joseph Smith40bffc22010-06-21 19:40:09 +000020#include <string.h>
21#include <cpu/cpu.h>
22#include <cpu/x86/mtrr.h>
23#include <cpu/x86/msr.h>
24#include <cpu/x86/lapic.h>
25#include <cpu/intel/microcode.h>
26#include <cpu/x86/cache.h>
Uwe Hermannaac8f662010-09-29 09:54:16 +000027#include <cpu/x86/name.h>
Joseph Smith40bffc22010-06-21 19:40:09 +000028
Edward O'Callaghan2c9d2cf2014-10-27 23:29:29 +110029static void model_68x_init(struct device *cpu)
Joseph Smith40bffc22010-06-21 19:40:09 +000030{
31 char processor_name[49];
32
33 /* Turn on caching if we haven't already */
34 x86_enable_cache();
35
36 /* Update the microcode */
Alexandru Gagniuc2c38f502013-12-06 23:14:54 -060037 intel_update_microcode_from_cbfs();
Joseph Smith40bffc22010-06-21 19:40:09 +000038
39 /* Print processor name */
40 fill_processor_name(processor_name);
41 printk(BIOS_INFO, "CPU: %s.\n", processor_name);
42
Joseph Smith40bffc22010-06-21 19:40:09 +000043 /* Setup MTRRs */
Sven Schnelleadfbcb792012-01-10 12:01:43 +010044 x86_setup_mtrrs();
Joseph Smith40bffc22010-06-21 19:40:09 +000045 x86_mtrr_check();
46
Joseph Smith40bffc22010-06-21 19:40:09 +000047 /* Enable the local cpu apics */
48 setup_lapic();
49}
50
51static struct device_operations cpu_dev_ops = {
52 .init = model_68x_init,
53};
54
Uwe Hermanncc0dc7f2010-10-04 20:43:55 +000055/*
56 * Intel Celeron Processor Identification Information
57 * http://www.intel.com/design/celeron/qit/update.pdf
58 *
59 * Intel Pentium III Processor Identification and Package Information
60 * http://www.intel.com/design/pentiumiii/qit/update.pdf
61 *
62 * Intel Pentium III Processor Specification Update
63 * http://download.intel.com/design/intarch/specupdt/24445358.pdf
64 *
65 * Mobile Intel Pentium III/III-M Processor Specification Update
66 * http://download.intel.com/design/intarch/specupdt/24530663.pdf
67 */
Joseph Smith40bffc22010-06-21 19:40:09 +000068static struct cpu_device_id cpu_table[] = {
69 { X86_VENDOR_INTEL, 0x0680 },
Uwe Hermanncc0dc7f2010-10-04 20:43:55 +000070 { X86_VENDOR_INTEL, 0x0681 }, /* PIII, cA2/cA2c/A2/BA2/PA2/MA2 */
71 { X86_VENDOR_INTEL, 0x0683 }, /* PIII/Celeron, cB0/cB0c/B0/BB0/PB0/MB0*/
72 { X86_VENDOR_INTEL, 0x0686 }, /* PIII/Celeron, cC0/C0/BC0/PC0/MC0 */
73 { X86_VENDOR_INTEL, 0x068a }, /* PIII/Celeron, cD0/D0/BD0/PD0 */
74
Joseph Smith40bffc22010-06-21 19:40:09 +000075 { 0, 0 },
76};
77
78static const struct cpu_driver driver __cpu_driver = {
79 .ops = &cpu_dev_ops,
80 .id_table = cpu_table,
81};