Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License as |
| 8 | * published by the Free Software Foundation; version 2 of |
| 9 | * the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 15 | */ |
| 16 | |
| 17 | #include <stdint.h> |
| 18 | #include <stdlib.h> |
| 19 | #include <cpu/cpu.h> |
| 20 | #include <cpu/x86/msr.h> |
Patrick Georgi | 644e83b | 2013-02-09 15:35:30 +0100 | [diff] [blame] | 21 | #include <cpu/intel/speedstep.h> |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 22 | #include "model_206ax.h" |
| 23 | |
Alexander Couzens | f251a6d | 2015-01-28 01:51:04 +0100 | [diff] [blame] | 24 | /* MSR Documentation based on |
| 25 | * "Sandy Bridge Processor Family BIOS Writer's Guide (BWG)" |
| 26 | * Document Number 504790 |
| 27 | * Revision 1.6.0, June 2012 */ |
| 28 | |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 29 | static void msr_set_bit(unsigned reg, unsigned bit) |
| 30 | { |
| 31 | msr_t msr = rdmsr(reg); |
| 32 | |
| 33 | if (bit < 32) { |
| 34 | if (msr.lo & (1 << bit)) |
| 35 | return; |
| 36 | msr.lo |= 1 << bit; |
| 37 | } else { |
| 38 | if (msr.hi & (1 << (bit - 32))) |
| 39 | return; |
| 40 | msr.hi |= 1 << (bit - 32); |
| 41 | } |
| 42 | |
| 43 | wrmsr(reg, msr); |
| 44 | } |
| 45 | |
| 46 | void intel_model_206ax_finalize_smm(void) |
| 47 | { |
Alexander Couzens | f251a6d | 2015-01-28 01:51:04 +0100 | [diff] [blame] | 48 | /* Lock C-State MSR */ |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 49 | msr_set_bit(MSR_PMG_CST_CONFIG_CONTROL, 15); |
| 50 | |
| 51 | /* Lock AES-NI only if supported */ |
| 52 | if (cpuid_ecx(1) & (1 << 25)) |
| 53 | msr_set_bit(MSR_FEATURE_CONFIG, 0); |
| 54 | |
Sameer Nanda | d16d576 | 2012-07-25 16:11:40 -0700 | [diff] [blame] | 55 | #ifdef LOCK_POWER_CONTROL_REGISTERS |
| 56 | /* |
| 57 | * Lock the power control registers. |
| 58 | * |
| 59 | * These registers can be left unlocked if modifying power |
| 60 | * limits from the OS is desirable. Modifying power limits |
| 61 | * from the OS can be especially useful for experimentation |
| 62 | * during early phases of system bringup while the thermal |
| 63 | * power envelope is being proven. |
| 64 | */ |
| 65 | |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 66 | msr_set_bit(MSR_PP0_CURRENT_CONFIG, 31); |
| 67 | msr_set_bit(MSR_PP1_CURRENT_CONFIG, 31); |
| 68 | msr_set_bit(MSR_PKG_POWER_LIMIT, 63); |
| 69 | msr_set_bit(MSR_PP0_POWER_LIMIT, 31); |
| 70 | msr_set_bit(MSR_PP1_POWER_LIMIT, 31); |
Sameer Nanda | d16d576 | 2012-07-25 16:11:40 -0700 | [diff] [blame] | 71 | #endif |
| 72 | |
Alexander Couzens | f251a6d | 2015-01-28 01:51:04 +0100 | [diff] [blame] | 73 | /* Lock TM interupts - route thermal events to all processors */ |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 74 | msr_set_bit(MSR_MISC_PWR_MGMT, 22); |
Alexander Couzens | f251a6d | 2015-01-28 01:51:04 +0100 | [diff] [blame] | 75 | |
| 76 | /* Lock memory configuration to protect SMM */ |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 77 | msr_set_bit(MSR_LT_LOCK_MEMORY, 0); |
| 78 | } |