| Sol Boucher | 8ccdeae | 2015-04-30 18:02:08 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright 2015 Google, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| Sol Boucher | 8ccdeae | 2015-04-30 18:02:08 -0700 | [diff] [blame] | 14 | */ |
| 15 | |
| 16 | #include <cbmem.h> |
| 17 | #include <stage_cache.h> |
| 18 | #include "haswell.h" |
| 19 | |
| 20 | void stage_cache_external_region(void **base, size_t *size) |
| 21 | { |
| 22 | /* The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET. |
| 23 | * The top of ram is defined to be the TSEG base address. */ |
| 24 | *size = RESERVED_SMM_SIZE; |
| 25 | *base = (void *)((uint32_t)cbmem_top() + RESERVED_SMM_OFFSET); |
| 26 | } |