blob: cd9ec5d51bf67765e9a8f35d342f773abdaebdcb [file] [log] [blame]
Aaron Durbin76c37002012-10-30 09:03:43 -05001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
Aaron Durbin76c37002012-10-30 09:03:43 -050014 */
15
16extern struct chip_operations cpu_intel_haswell_ops;
17
18/* Magic value used to locate this chip in the device tree */
19#define SPEEDSTEP_APIC_MAGIC 0xACAC
20
21struct cpu_intel_haswell_config {
22 u8 disable_acpi; /* Do not generate CPU ACPI tables */
23
Aaron Durbin76c37002012-10-30 09:03:43 -050024 int c1_battery; /* ACPI C1 on Battery Power */
25 int c2_battery; /* ACPI C2 on Battery Power */
26 int c3_battery; /* ACPI C3 on Battery Power */
27
28 int c1_acpower; /* ACPI C1 on AC Power */
29 int c2_acpower; /* ACPI C2 on AC Power */
30 int c3_acpower; /* ACPI C3 on AC Power */
31
32 int tcc_offset; /* TCC Activation Offset */
33};