Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2011 Google Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 14 | */ |
| 15 | |
| 16 | #include <stdint.h> |
| 17 | #include <arch/cpu.h> |
| 18 | #include <cpu/x86/cache.h> |
| 19 | #include <cpu/x86/msr.h> |
| 20 | #include <cpu/x86/mtrr.h> |
| 21 | #include <arch/io.h> |
Patrick Georgi | 546953c | 2014-11-29 10:38:17 +0100 | [diff] [blame] | 22 | #include <halt.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 23 | |
| 24 | #include <cpu/intel/microcode/microcode.c> |
| 25 | #include "haswell.h" |
| 26 | |
| 27 | #if CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT |
| 28 | /* Needed for RCBA access to set Soft Reset Data register */ |
| 29 | #include <southbridge/intel/lynxpoint/pch.h> |
| 30 | #else |
| 31 | #error "CPU must be paired with Intel LynxPoint southbridge" |
| 32 | #endif |
| 33 | |
| 34 | static void set_var_mtrr( |
| 35 | unsigned reg, unsigned base, unsigned size, unsigned type) |
| 36 | |
| 37 | { |
| 38 | /* Bit Bit 32-35 of MTRRphysMask should be set to 1 */ |
| 39 | /* FIXME: It only support 4G less range */ |
| 40 | msr_t basem, maskm; |
| 41 | basem.lo = base | type; |
| 42 | basem.hi = 0; |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 43 | wrmsr(MTRR_PHYS_BASE(reg), basem); |
| 44 | maskm.lo = ~(size - 1) | MTRR_PHYS_MASK_VALID; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 45 | maskm.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1; |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 46 | wrmsr(MTRR_PHYS_MASK(reg), maskm); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 47 | } |
| 48 | |
| 49 | static void enable_rom_caching(void) |
| 50 | { |
| 51 | msr_t msr; |
| 52 | |
| 53 | disable_cache(); |
Kyösti Mälkki | bbf013c | 2014-01-06 11:08:01 +0200 | [diff] [blame] | 54 | set_var_mtrr(1, CACHE_ROM_BASE, CACHE_ROM_SIZE, MTRR_TYPE_WRPROT); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 55 | enable_cache(); |
| 56 | |
| 57 | /* Enable Variable MTRRs */ |
| 58 | msr.hi = 0x00000000; |
| 59 | msr.lo = 0x00000800; |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 60 | wrmsr(MTRR_DEF_TYPE_MSR, msr); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 61 | } |
| 62 | |
| 63 | static void set_flex_ratio_to_tdp_nominal(void) |
| 64 | { |
| 65 | msr_t flex_ratio, msr; |
| 66 | u32 soft_reset; |
| 67 | u8 nominal_ratio; |
| 68 | |
| 69 | /* Check for Flex Ratio support */ |
| 70 | flex_ratio = rdmsr(MSR_FLEX_RATIO); |
| 71 | if (!(flex_ratio.lo & FLEX_RATIO_EN)) |
| 72 | return; |
| 73 | |
| 74 | /* Check for >0 configurable TDPs */ |
| 75 | msr = rdmsr(MSR_PLATFORM_INFO); |
| 76 | if (((msr.hi >> 1) & 3) == 0) |
| 77 | return; |
| 78 | |
| 79 | /* Use nominal TDP ratio for flex ratio */ |
| 80 | msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); |
| 81 | nominal_ratio = msr.lo & 0xff; |
| 82 | |
| 83 | /* See if flex ratio is already set to nominal TDP ratio */ |
| 84 | if (((flex_ratio.lo >> 8) & 0xff) == nominal_ratio) |
| 85 | return; |
| 86 | |
| 87 | /* Set flex ratio to nominal TDP ratio */ |
| 88 | flex_ratio.lo &= ~0xff00; |
| 89 | flex_ratio.lo |= nominal_ratio << 8; |
| 90 | flex_ratio.lo |= FLEX_RATIO_LOCK; |
| 91 | wrmsr(MSR_FLEX_RATIO, flex_ratio); |
| 92 | |
| 93 | /* Set flex ratio in soft reset data register bits 11:6. |
| 94 | * RCBA region is enabled in southbridge bootblock */ |
| 95 | soft_reset = RCBA32(SOFT_RESET_DATA); |
| 96 | soft_reset &= ~(0x3f << 6); |
| 97 | soft_reset |= (nominal_ratio & 0x3f) << 6; |
| 98 | RCBA32(SOFT_RESET_DATA) = soft_reset; |
| 99 | |
| 100 | /* Set soft reset control to use register value */ |
| 101 | RCBA32_OR(SOFT_RESET_CTRL, 1); |
| 102 | |
| 103 | /* Issue warm reset, will be "CPU only" due to soft reset data */ |
| 104 | outb(0x0, 0xcf9); |
| 105 | outb(0x6, 0xcf9); |
Patrick Georgi | 546953c | 2014-11-29 10:38:17 +0100 | [diff] [blame] | 106 | halt(); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 107 | } |
| 108 | |
Aaron Durbin | 5afca13 | 2013-05-30 10:40:54 -0500 | [diff] [blame] | 109 | static void check_for_clean_reset(void) |
| 110 | { |
| 111 | msr_t msr; |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 112 | msr = rdmsr(MTRR_DEF_TYPE_MSR); |
Aaron Durbin | 5afca13 | 2013-05-30 10:40:54 -0500 | [diff] [blame] | 113 | |
| 114 | /* Use the MTRR default type MSR as a proxy for detecting INIT#. |
| 115 | * Reset the system if any known bits are set in that MSR. That is |
| 116 | * an indication of the CPU not being properly reset. */ |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 117 | if (msr.lo & (MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN)) { |
Aaron Durbin | 5afca13 | 2013-05-30 10:40:54 -0500 | [diff] [blame] | 118 | outb(0x0, 0xcf9); |
| 119 | outb(0x6, 0xcf9); |
Patrick Georgi | 546953c | 2014-11-29 10:38:17 +0100 | [diff] [blame] | 120 | halt(); |
Aaron Durbin | 5afca13 | 2013-05-30 10:40:54 -0500 | [diff] [blame] | 121 | } |
| 122 | } |
| 123 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 124 | static void bootblock_cpu_init(void) |
| 125 | { |
| 126 | /* Set flex ratio and reset if needed */ |
| 127 | set_flex_ratio_to_tdp_nominal(); |
Aaron Durbin | 5afca13 | 2013-05-30 10:40:54 -0500 | [diff] [blame] | 128 | check_for_clean_reset(); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 129 | enable_rom_caching(); |
| 130 | intel_update_microcode_from_cbfs(); |
| 131 | } |