Martin Roth | 5856240 | 2015-10-11 10:36:26 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2011 Google Inc. |
| 5 | * Copyright (C) 2013-2014 Sage Electronic Engineering LLC. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Martin Roth | 5856240 | 2015-10-11 10:36:26 +0200 | [diff] [blame] | 15 | */ |
| 16 | |
| 17 | #include <stdint.h> |
| 18 | #include <arch/cpu.h> |
| 19 | #include <cpu/x86/cache.h> |
David Guckian | 5f06d53 | 2015-11-09 16:19:18 +0000 | [diff] [blame] | 20 | #include <cpu/intel/microcode/microcode.c> |
Martin Roth | 5856240 | 2015-10-11 10:36:26 +0200 | [diff] [blame] | 21 | #include <cpu/x86/msr.h> |
| 22 | #include <cpu/x86/mtrr.h> |
| 23 | #include <arch/io.h> |
| 24 | #include <reset.h> |
| 25 | #include <southbridge/intel/fsp_rangeley/soc.h> |
| 26 | |
| 27 | #include "model_406dx.h" |
| 28 | |
| 29 | /* |
| 30 | * check for a warm reset and do a hard reset instead. |
| 31 | */ |
| 32 | static void check_for_warm_reset(void) |
| 33 | { |
| 34 | |
| 35 | /* |
| 36 | * Check if INIT# is asserted by port 0xCF9 and whether RCBA has been set. |
| 37 | * If either is true, then this is a warm reset so execute a Hard Reset |
| 38 | */ |
| 39 | if ( (inb(0xcf9) == 0x04) || |
| 40 | (pci_io_read_config32(SOC_LPC_DEV, RCBA) & RCBA_ENABLE) ) { |
| 41 | outb(0x00, 0xcf9); |
| 42 | outb(0x06, 0xcf9); |
| 43 | } |
| 44 | } |
| 45 | |
| 46 | static void set_var_mtrr(int reg, uint32_t base, uint32_t size, int type) |
| 47 | { |
Martin Roth | 5856240 | 2015-10-11 10:36:26 +0200 | [diff] [blame] | 48 | /* Bit Bit 32-35 of MTRRphysMask should be set to 1 */ |
| 49 | msr_t basem, maskm; |
| 50 | basem.lo = base | type; |
| 51 | basem.hi = 0; |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 52 | wrmsr(MTRR_PHYS_BASE(reg), basem); |
| 53 | maskm.lo = ~(size - 1) | MTRR_PHYS_MASK_VALID; |
Martin Roth | 5856240 | 2015-10-11 10:36:26 +0200 | [diff] [blame] | 54 | maskm.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1; |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 55 | wrmsr(MTRR_PHYS_MASK(reg), maskm); |
Martin Roth | 5856240 | 2015-10-11 10:36:26 +0200 | [diff] [blame] | 56 | } |
| 57 | |
| 58 | static void enable_rom_caching(void) |
| 59 | { |
| 60 | msr_t msr; |
| 61 | |
| 62 | disable_cache(); |
| 63 | set_var_mtrr(1, 0xffffffff - CACHE_ROM_SIZE + 1, |
| 64 | CACHE_ROM_SIZE, MTRR_TYPE_WRPROT); |
| 65 | enable_cache(); |
| 66 | |
| 67 | /* Enable Variable MTRRs */ |
| 68 | msr.hi = 0x00000000; |
| 69 | msr.lo = 0x00000800; |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 70 | wrmsr(MTRR_DEF_TYPE_MSR, msr); |
Martin Roth | 5856240 | 2015-10-11 10:36:26 +0200 | [diff] [blame] | 71 | } |
| 72 | |
| 73 | static void set_no_evict_mode_msr(void) |
| 74 | { |
| 75 | msr_t msr; |
| 76 | msr.hi = 0x00000000; |
| 77 | msr.lo = 0x00000000; |
| 78 | |
| 79 | wrmsr(MSR_NO_EVICT_MODE, msr); |
| 80 | } |
| 81 | |
| 82 | static void bootblock_cpu_init(void) |
| 83 | { |
| 84 | /* Check for Warm Reset */ |
| 85 | check_for_warm_reset(); |
David Guckian | 5f06d53 | 2015-11-09 16:19:18 +0000 | [diff] [blame] | 86 | |
| 87 | /* Load microcode before any caching. */ |
| 88 | intel_update_microcode_from_cbfs(); |
| 89 | |
Martin Roth | 5856240 | 2015-10-11 10:36:26 +0200 | [diff] [blame] | 90 | enable_rom_caching(); |
| 91 | set_no_evict_mode_msr(); |
| 92 | } |