| Andrew Wu | 52e665b | 2013-06-19 18:55:08 +0800 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2013 DMP Electronics Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| Andrew Wu | 52e665b | 2013-06-19 18:55:08 +0800 | [diff] [blame] | 14 | */ |
| 15 | |
| 16 | #include "config.h" |
| 17 | |
| 18 | /* |
| 19 | PLL Freq = 25 * NS /(MS * 2^RS) |
| 20 | CPU Freq = PLL/(CPU_DIV+2) |
| 21 | DRAM Freq = PLL/2(DRAM_DIV+1) |
| 22 | |
| 23 | DDR3 |
| 24 | CPU/DRAM/PCI B6 B7 BB BC BD BF |
| 25 | 200/200/33 30 03 0F 02 8F 07 |
| 26 | 300/300/33 48 03 0F 02 1F 07 |
| 27 | 300/300/33 48 03 0F 3A DF 07 ; write leveling disable, cpu bypass disable |
| 28 | 300/300/33 48 03 0F 22 3F 07 ; cpu bypass disable |
| 29 | 300/300/100 48 03 23 02 7F 07 |
| 30 | 400/200/33 60 43 0F 02 3F 07 ; without 200MHz timing, so set 300MHz timing |
| 31 | 400/200/100 60 43 23 02 4F 07 |
| 32 | 400/400/33 60 03 0F 02 BF 09 |
| 33 | 500/250/33 50 42 0F 02 DF 07 |
| 34 | 500/500/33 78 03 0F 02 4F 09 |
| 35 | 400/300/33 90 53 0F 02 3F 07 |
| 36 | 400/300/33 90 53 0F 1A DF 07 ; write leveling/gate training disable |
| 37 | 400/300/100 90 53 23 02 9F 07 |
| 38 | 444/333/33 A0 53 0F 02 5F 08 |
| 39 | 466/350/33 A8 53 0F 02 DF 09 |
| 40 | 500/375/33 B4 53 0F 02 AF 09 |
| 41 | */ |
| 42 | |
| 43 | #if CONFIG_PLL_200_200_33 |
| 44 | // 200/200/33 30 03 0F 02 8F 07 |
| 45 | byte_fffb6 = 0x30 |
| 46 | byte_fffb7 = 0x03 |
| 47 | byte_fffbb = 0x0f |
| 48 | byte_fffbc = 0x02 |
| 49 | byte_fffbe = 0xff |
| 50 | byte_fffbf = 0x07 |
| 51 | #elif CONFIG_PLL_300_300_33 |
| 52 | // 300/300/33 48 03 0F 02 1F 07 |
| 53 | byte_fffb6 = 0x48 |
| 54 | byte_fffb7 = 0x03 |
| 55 | byte_fffbb = 0x0f |
| 56 | byte_fffbc = 0x02 |
| 57 | byte_fffbe = 0xff |
| 58 | byte_fffbf = 0x07 |
| 59 | #elif CONFIG_PLL_300_300_100 |
| 60 | // 300/300/100 48 03 23 02 7F 07 |
| 61 | byte_fffb6 = 0x48 |
| 62 | byte_fffb7 = 0x03 |
| 63 | byte_fffbb = 0x23 |
| 64 | byte_fffbc = 0x02 |
| 65 | byte_fffbe = 0xff |
| 66 | byte_fffbf = 0x07 |
| 67 | #elif CONFIG_PLL_400_200_33 |
| 68 | // 400/200/33 60 43 0F 02 3F 07 ; without 200MHz timing, so set 300MHz timing |
| 69 | byte_fffb6 = 0x60 |
| 70 | byte_fffb7 = 0x43 |
| 71 | byte_fffbb = 0x0f |
| 72 | byte_fffbc = 0x02 |
| 73 | byte_fffbe = 0xff |
| 74 | byte_fffbf = 0x07 |
| 75 | #elif CONFIG_PLL_400_200_100 |
| 76 | // 400/200/100 60 43 23 02 4F 07 |
| 77 | byte_fffb6 = 0x60 |
| 78 | byte_fffb7 = 0x43 |
| 79 | byte_fffbb = 0x23 |
| 80 | byte_fffbc = 0x02 |
| 81 | byte_fffbe = 0xff |
| 82 | byte_fffbf = 0x07 |
| 83 | #elif CONFIG_PLL_400_400_33 |
| 84 | // 400/400/33 60 03 0F 02 BF 09 |
| 85 | byte_fffb6 = 0x60 |
| 86 | byte_fffb7 = 0x03 |
| 87 | byte_fffbb = 0x0f |
| 88 | byte_fffbc = 0x02 |
| 89 | byte_fffbe = 0xff |
| 90 | byte_fffbf = 0x09 |
| 91 | #elif CONFIG_PLL_500_250_33 |
| 92 | // 500/250/33 50 42 0F 02 DF 07 |
| 93 | byte_fffb6 = 0x50 |
| 94 | byte_fffb7 = 0x42 |
| 95 | byte_fffbb = 0x0f |
| 96 | byte_fffbc = 0x02 |
| 97 | byte_fffbe = 0xff |
| 98 | byte_fffbf = 0x07 |
| 99 | #elif CONFIG_PLL_500_500_33 |
| 100 | // 500/500/33 78 03 0F 02 4F 09 |
| 101 | byte_fffb6 = 0x78 |
| 102 | byte_fffb7 = 0x03 |
| 103 | byte_fffbb = 0x0f |
| 104 | byte_fffbc = 0x02 |
| 105 | byte_fffbe = 0xff |
| 106 | byte_fffbf = 0x09 |
| 107 | #elif CONFIG_PLL_400_300_33 |
| 108 | // 400/300/33 90 53 0F 02 3F 07 |
| 109 | byte_fffb6 = 0x90 |
| 110 | byte_fffb7 = 0x53 |
| 111 | byte_fffbb = 0x0f |
| 112 | byte_fffbc = 0x02 |
| 113 | byte_fffbe = 0xff |
| 114 | byte_fffbf = 0x07 |
| 115 | #elif CONFIG_PLL_400_300_100 |
| 116 | // 400/300/100 90 53 23 02 9F 07 |
| 117 | byte_fffb6 = 0x90 |
| 118 | byte_fffb7 = 0x53 |
| 119 | byte_fffbb = 0x23 |
| 120 | byte_fffbc = 0x02 |
| 121 | byte_fffbe = 0xff |
| 122 | byte_fffbf = 0x07 |
| 123 | #elif CONFIG_PLL_444_333_33 |
| 124 | // 444/333/33 A0 53 0F 02 5F 08 |
| 125 | byte_fffb6 = 0xa0 |
| 126 | byte_fffb7 = 0x53 |
| 127 | byte_fffbb = 0x0f |
| 128 | byte_fffbc = 0x02 |
| 129 | byte_fffbe = 0xff |
| 130 | byte_fffbf = 0x08 |
| 131 | #elif CONFIG_PLL_466_350_33 |
| 132 | // 466/350/33 A8 53 0F 02 DF 09 |
| 133 | byte_fffb6 = 0xa8 |
| 134 | byte_fffb7 = 0x53 |
| 135 | byte_fffbb = 0x0f |
| 136 | byte_fffbc = 0x02 |
| 137 | byte_fffbe = 0xff |
| 138 | byte_fffbf = 0x09 |
| 139 | #elif CONFIG_PLL_500_375_33 |
| 140 | // 500/375/33 B4 53 0F 02 AF 09 |
| 141 | byte_fffb6 = 0xb4 |
| 142 | byte_fffb7 = 0x53 |
| 143 | byte_fffbb = 0x0f |
| 144 | byte_fffbc = 0x02 |
| 145 | byte_fffbe = 0xff |
| 146 | byte_fffbf = 0x09 |
| 147 | #else |
| 148 | #error Error Strap PLL config. |
| 149 | #endif |
| 150 | |
| 151 | tmp_sum = byte_fffb6 + byte_fffb7 + byte_fffbb + byte_fffbc |
| 152 | pll_checksum = ((tmp_sum >> 8) & 0x3) + ((tmp_sum >> 4) & 0x0f) + (tmp_sum & 0x0f) |
| 153 | |
| 154 | byte_fffbd = ((pll_checksum & 0x0f) << 4) | 0x0f |
| 155 | |
| 156 | .section ".a9123_crossbar_config", "a", @progbits |
| 157 | |
| 158 | .skip 0x3fdf0 - 0x3fd00, 0xff |
| 159 | |
| 160 | .previous |
| 161 | |
| 162 | .section ".a9123_strap_1", "a", @progbits |
| 163 | |
| 164 | .byte byte_fffb6, byte_fffb7 |
| 165 | |
| 166 | .previous |
| 167 | |
| 168 | .section ".a9123_strap_2", "a", @progbits |
| 169 | |
| 170 | .byte byte_fffbb, byte_fffbc, byte_fffbd, byte_fffbe, byte_fffbf |
| 171 | |
| 172 | .previous |