Stefan Reinauer | 9839cbd | 2010-04-21 20:06:10 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 3 | * |
Stefan Reinauer | 9839cbd | 2010-04-21 20:06:10 +0000 | [diff] [blame] | 4 | * Copyright (C) 2010 coresystems GmbH |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Stefan Reinauer | 9839cbd | 2010-04-21 20:06:10 +0000 | [diff] [blame] | 14 | */ |
| 15 | |
Stefan Reinauer | 4e169f9 | 2010-04-22 00:52:42 +0000 | [diff] [blame] | 16 | #include <stdlib.h> |
Edwin Beasant | f333ba0 | 2010-06-10 15:24:57 +0000 | [diff] [blame] | 17 | #include "cpu/x86/msr.h" |
Stefan Reinauer | 4e169f9 | 2010-04-22 00:52:42 +0000 | [diff] [blame] | 18 | |
Edwin Beasant | f333ba0 | 2010-06-10 15:24:57 +0000 | [diff] [blame] | 19 | static const msrinit_t msr_table[] = |
Stefan Reinauer | 9839cbd | 2010-04-21 20:06:10 +0000 | [diff] [blame] | 20 | { |
Nils Jacobs | eb84f6a | 2012-01-09 20:27:07 +0100 | [diff] [blame] | 21 | {CPU_RCONF_DEFAULT, {.hi = 0x24fffc00,.lo = 0x0000A000}}, /* Setup access to cache under 1MB. |
Stefan Reinauer | 9839cbd | 2010-04-21 20:06:10 +0000 | [diff] [blame] | 22 | * Rom Properties: Write Serialize, WriteProtect. |
| 23 | * RomBase: 0xFFFC0 |
Nils Jacobs | eb84f6a | 2012-01-09 20:27:07 +0100 | [diff] [blame] | 24 | * SysTop to RomBase Properties: Write Back. |
Stefan Reinauer | 9839cbd | 2010-04-21 20:06:10 +0000 | [diff] [blame] | 25 | * SysTop: 0x000A0 |
| 26 | * System Memory Properties: (Write Back) */ |
| 27 | {CPU_RCONF_A0_BF, {.hi = 0x00000000,.lo = 0x00000000}}, /* 0xA0000-0xBFFFF : (Write Back) */ |
| 28 | {CPU_RCONF_C0_DF, {.hi = 0x00000000,.lo = 0x00000000}}, /* 0xC0000-0xDFFFF : (Write Back) */ |
| 29 | {CPU_RCONF_E0_FF, {.hi = 0x00000000,.lo = 0x00000000}}, /* 0xE0000-0xFFFFF : (Write Back) */ |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 30 | |
Stefan Reinauer | 9839cbd | 2010-04-21 20:06:10 +0000 | [diff] [blame] | 31 | /* Setup access to memory under 1MB. Note: VGA hole at 0xA0000-0xBFFFF */ |
| 32 | {MSR_GLIU0_BASE1, {.hi = 0x20000000,.lo = 0x000fff80}}, // 0x00000-0x7FFFF |
| 33 | {MSR_GLIU0_BASE2, {.hi = 0x20000000,.lo = 0x080fffe0}}, // 0x80000-0x9FFFF |
| 34 | {MSR_GLIU0_SHADOW, {.hi = 0x2000FFFF,.lo = 0xFFFF0003}}, // 0xC0000-0xFFFFF |
| 35 | {MSR_GLIU1_BASE1, {.hi = 0x20000000,.lo = 0x000fff80}}, // 0x00000-0x7FFFF |
| 36 | {MSR_GLIU1_BASE2, {.hi = 0x20000000,.lo = 0x080fffe0}}, // 0x80000-0x9FFFF |
| 37 | {MSR_GLIU1_SHADOW, {.hi = 0x2000FFFF,.lo = 0xFFFF0003}}, // 0xC0000-0xFFFFF |
Aurelien Guillaume | 34697d6 | 2010-09-07 07:43:10 +0000 | [diff] [blame] | 38 | |
| 39 | /* Pre-setup access to memory above 1Mb. Here we set up about 500Mb of memory. |
| 40 | * It doesn't really matter in fact how much, however, because the only usage |
Furquan Shaikh | 20f25dd | 2014-04-22 10:41:05 -0700 | [diff] [blame] | 41 | * of this extended memory will be to host the ramstage stage at RAMBASE, |
Aurelien Guillaume | 34697d6 | 2010-09-07 07:43:10 +0000 | [diff] [blame] | 42 | * currently 1Mb. |
| 43 | * These registers will be set to their correct value by the Northbridge init code. |
Stefan Reinauer | 5ff7c13 | 2011-10-31 12:56:45 -0700 | [diff] [blame] | 44 | * |
Furquan Shaikh | 20f25dd | 2014-04-22 10:41:05 -0700 | [diff] [blame] | 45 | * WARNING: if ramstage could not be loaded, these registers are probably |
Aurelien Guillaume | 34697d6 | 2010-09-07 07:43:10 +0000 | [diff] [blame] | 46 | * incorrectly set here. You may comment the following two lines and set RAMBASE |
| 47 | * to 0x4000 to revert to the previous behavior for LX-boards. |
| 48 | */ |
| 49 | {MSR_GLIU0_SYSMEM, {.hi = 0x2000001F,.lo = 0x6BF00100}}, // 0x100000-0x1F6BF000 |
| 50 | {MSR_GLIU1_SYSMEM, {.hi = 0x2000001F,.lo = 0x6BF00100}}, // 0x100000-0x1F6BF000 |
Stefan Reinauer | 9839cbd | 2010-04-21 20:06:10 +0000 | [diff] [blame] | 51 | }; |
| 52 | |
| 53 | static void msr_init(void) |
| 54 | { |
| 55 | int i; |
| 56 | for (i = 0; i < ARRAY_SIZE(msr_table); i++) |
Edwin Beasant | f333ba0 | 2010-06-10 15:24:57 +0000 | [diff] [blame] | 57 | wrmsr(msr_table[i].index, msr_table[i].msr); |
Stefan Reinauer | 9839cbd | 2010-04-21 20:06:10 +0000 | [diff] [blame] | 58 | } |