Jordan Crouse | 6818245 | 2007-05-03 21:36:51 +0000 | [diff] [blame] | 1 | /* |
Stefan Reinauer | 7e61e45 | 2008-01-18 10:35:56 +0000 | [diff] [blame] | 2 | * This file is part of the coreboot project. |
Jordan Crouse | 6818245 | 2007-05-03 21:36:51 +0000 | [diff] [blame] | 3 | * |
| 4 | * Copyright (C) 2006 Indrek Kruusa <indrek.kruusa@artecdesign.ee> |
| 5 | * Copyright (C) 2006 Ronald G. Minnich <rminnich@gmail.com> |
| 6 | * Copyright (C) 2007 Advanced Micro Devices, Inc. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; either version 2 of the License, or |
| 11 | * (at your option) any later version. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
Jordan Crouse | 6818245 | 2007-05-03 21:36:51 +0000 | [diff] [blame] | 17 | */ |
| 18 | |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 19 | #include <console/console.h> |
| 20 | #include <arch/io.h> |
| 21 | #include <stdint.h> |
| 22 | #include <device/device.h> |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 23 | #include <stdlib.h> |
| 24 | #include <string.h> |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 25 | #include <cpu/x86/msr.h> |
Marc Jones | bc8176c | 2007-05-04 18:24:55 +0000 | [diff] [blame] | 26 | #include <cpu/amd/lxdef.h> |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 27 | |
Edward O'Callaghan | cd2c124 | 2014-08-09 15:51:19 +1000 | [diff] [blame] | 28 | /** |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 29 | * |
| 30 | * pcideadlock |
| 31 | * |
| 32 | * Bugtool #465 and #609 |
| 33 | * PCI cache deadlock |
Edward O'Callaghan | cd2c124 | 2014-08-09 15:51:19 +1000 | [diff] [blame] | 34 | * There is also fix code in cache and PCI functions. |
| 35 | * This bug is very is pervasive. |
| 36 | */ |
Jordan Crouse | 9934b81 | 2007-05-10 18:32:28 +0000 | [diff] [blame] | 37 | static void pcideadlock(void) |
| 38 | { |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 39 | msr_t msr; |
| 40 | |
| 41 | /* |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 42 | * forces serialization of all load misses. Setting this bit prevents the |
| 43 | * DM pipe from backing up if a read request has to be held up waiting |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 44 | * for PCI writes to complete. |
Jordan Crouse | 9934b81 | 2007-05-10 18:32:28 +0000 | [diff] [blame] | 45 | */ |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 46 | msr = rdmsr(CPU_DM_CONFIG0); |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 47 | msr.lo |= DM_CONFIG0_LOWER_MISSER_SET; |
| 48 | wrmsr(CPU_DM_CONFIG0, msr); |
| 49 | |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 50 | /* write serialize memory hole to PCI. Need to unWS when something is |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 51 | * shadowed regardless of cachablility. |
| 52 | */ |
| 53 | msr.lo = 0x021212121; |
| 54 | msr.hi = 0x021212121; |
Jordan Crouse | 9934b81 | 2007-05-10 18:32:28 +0000 | [diff] [blame] | 55 | wrmsr(CPU_RCONF_A0_BF, msr); |
| 56 | wrmsr(CPU_RCONF_C0_DF, msr); |
| 57 | wrmsr(CPU_RCONF_E0_FF, msr); |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 58 | } |
| 59 | |
Edward O'Callaghan | cd2c124 | 2014-08-09 15:51:19 +1000 | [diff] [blame] | 60 | /** |
| 61 | * DisableMemoryReorder |
| 62 | * |
| 63 | * PBZ 3659: |
| 64 | * The MC reordered transactions incorrectly and breaks coherency. |
| 65 | * Disable reordering and take a potential performance hit. |
| 66 | * This is safe to do here and not in MC init since there is nothing |
| 67 | * to maintain coherency with and the cache is not enabled yet. |
| 68 | */ |
Jordan Crouse | 9934b81 | 2007-05-10 18:32:28 +0000 | [diff] [blame] | 69 | static void disablememoryreadorder(void) |
| 70 | { |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 71 | msr_t msr; |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 72 | |
Marc Jones | bc8176c | 2007-05-04 18:24:55 +0000 | [diff] [blame] | 73 | msr = rdmsr(MC_CF8F_DATA); |
Jordan Crouse | 9934b81 | 2007-05-10 18:32:28 +0000 | [diff] [blame] | 74 | msr.hi |= CF8F_UPPER_REORDER_DIS_SET; |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 75 | wrmsr(MC_CF8F_DATA, msr); |
| 76 | } |
| 77 | |
Marc Jones | bc8176c | 2007-05-04 18:24:55 +0000 | [diff] [blame] | 78 | /* For cpu version C3. Should be the only released version */ |
Jordan Crouse | 9934b81 | 2007-05-10 18:32:28 +0000 | [diff] [blame] | 79 | void cpubug(void) |
| 80 | { |
| 81 | pcideadlock(); |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 82 | disablememoryreadorder(); |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 83 | printk(BIOS_DEBUG, "Done cpubug fixes \n"); |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 84 | } |