Ronald G. Minnich | 45f6c5e | 2006-04-10 16:40:19 +0000 | [diff] [blame] | 1 | |
Nils Jacobs | e98db79 | 2010-11-03 13:21:41 +0000 | [diff] [blame] | 2 | /* cpuRegInit */ |
Nils Jacobs | e474070 | 2010-07-26 23:46:25 +0000 | [diff] [blame] | 3 | void cpuRegInit (void) |
| 4 | { |
Ronald G. Minnich | 526b2c4 | 2006-04-10 16:14:19 +0000 | [diff] [blame] | 5 | int msrnum; |
| 6 | msr_t msr; |
Nils Jacobs | e98db79 | 2010-11-03 13:21:41 +0000 | [diff] [blame] | 7 | /* The following is only for diagnostics mode; do not use for OLPC */ |
Ronald G. Minnich | fb93749 | 2006-06-10 22:57:15 +0000 | [diff] [blame] | 8 | if (0) { |
Nils Jacobs | e98db79 | 2010-11-03 13:21:41 +0000 | [diff] [blame] | 9 | /* Set Diagnostic Mode */ |
Ronald G. Minnich | d3ba4aa | 2006-05-02 03:07:11 +0000 | [diff] [blame] | 10 | msrnum = CPU_GLD_MSR_DIAG; |
| 11 | msr.hi = 0; |
| 12 | msr.lo = DIAG_SEL1_SET | DIAG_SET0_SET; |
| 13 | wrmsr(msrnum, msr); |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 14 | |
Nils Jacobs | e98db79 | 2010-11-03 13:21:41 +0000 | [diff] [blame] | 15 | /* Set up GLCP to grab BTM data. */ |
Nils Jacobs | 3344743 | 2010-12-26 05:16:47 +0000 | [diff] [blame] | 16 | msrnum = GLCP_DBGOUT; /* GLCP_DBGOUT MSR */ |
Ronald G. Minnich | d3ba4aa | 2006-05-02 03:07:11 +0000 | [diff] [blame] | 17 | msr.hi = 0x0; |
Martin Roth | 4c3ab73 | 2013-07-08 16:23:54 -0600 | [diff] [blame] | 18 | msr.lo = 0x08; /* reset value (SCOPE_SEL = 0) causes FIFO to shift out, */ |
Nils Jacobs | e98db79 | 2010-11-03 13:21:41 +0000 | [diff] [blame] | 19 | wrmsr(msrnum, msr); /* exchange it to anything else to prevent this */ |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 20 | |
Nils Jacobs | e98db79 | 2010-11-03 13:21:41 +0000 | [diff] [blame] | 21 | /* Turn off debug clock */ |
Nils Jacobs | 3344743 | 2010-12-26 05:16:47 +0000 | [diff] [blame] | 22 | msrnum = GLCP_DBGCLKCTL; /* DBG_CLK_CTL */ |
Nils Jacobs | 1c6d4e6 | 2010-12-26 05:12:49 +0000 | [diff] [blame] | 23 | msr.lo = 0x00; /* No clock */ |
Ronald G. Minnich | d3ba4aa | 2006-05-02 03:07:11 +0000 | [diff] [blame] | 24 | msr.hi = 0x00; |
| 25 | wrmsr(msrnum, msr); |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 26 | |
Nils Jacobs | e98db79 | 2010-11-03 13:21:41 +0000 | [diff] [blame] | 27 | /* Set debug clock to CPU */ |
Nils Jacobs | 3344743 | 2010-12-26 05:16:47 +0000 | [diff] [blame] | 28 | msrnum = GLCP_DBGCLKCTL; /* DBG_CLK_CTL */ |
Nils Jacobs | e98db79 | 2010-11-03 13:21:41 +0000 | [diff] [blame] | 29 | msr.lo = 0x01; /* CPU CLOCK */ |
Ronald G. Minnich | d3ba4aa | 2006-05-02 03:07:11 +0000 | [diff] [blame] | 30 | msr.hi = 0x00; |
| 31 | wrmsr(msrnum, msr); |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 32 | |
Nils Jacobs | e98db79 | 2010-11-03 13:21:41 +0000 | [diff] [blame] | 33 | /* Set fifo ctl to BTM bits wide */ |
Nils Jacobs | 3344743 | 2010-12-26 05:16:47 +0000 | [diff] [blame] | 34 | msrnum = GLCP_FIFOCTL; /* FIFO_CTL */ |
Nils Jacobs | e98db79 | 2010-11-03 13:21:41 +0000 | [diff] [blame] | 35 | msr.lo = 0x003880000; /* Bit [25:24] are size (11=BTM, 10 = 64 bit, 01= 32 bit, 00 = 16bit) */ |
| 36 | wrmsr(msrnum, msr); /* Bit [23:21] are position (100 = CPU downto0) */ |
| 37 | /* Bit [19] sets it up in slow data mode. */ |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 38 | |
Nils Jacobs | e98db79 | 2010-11-03 13:21:41 +0000 | [diff] [blame] | 39 | /* enable fifo loading - BTM sizing will constrain */ |
| 40 | /* only valid BTM packets to load - this action should always be on */ |
| 41 | msrnum = 0x04C00006F; /* GLCP ACTION7 - load fifo */ |
| 42 | msr.lo = 0x00000F000; /* Any nibble all 1's will always trigger */ |
Ronald G. Minnich | d3ba4aa | 2006-05-02 03:07:11 +0000 | [diff] [blame] | 43 | msr.hi = 0x000000000; |
| 44 | wrmsr(msrnum, msr); |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 45 | |
Nils Jacobs | e98db79 | 2010-11-03 13:21:41 +0000 | [diff] [blame] | 46 | /* start storing diag data in the fifo */ |
| 47 | msrnum = 0x04C00005F; /* DIAG CTL */ |
| 48 | msr.lo = 0x080000000; /* enable actions */ |
| 49 | msr.hi = 0x000000000; |
Ronald G. Minnich | d3ba4aa | 2006-05-02 03:07:11 +0000 | [diff] [blame] | 50 | wrmsr(msrnum, msr); |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 51 | |
Nils Jacobs | e98db79 | 2010-11-03 13:21:41 +0000 | [diff] [blame] | 52 | /* Set up delay on data lines, so that the hold time */ |
| 53 | /* is 1 ns. */ |
Nils Jacobs | 3344743 | 2010-12-26 05:16:47 +0000 | [diff] [blame] | 54 | msrnum = GLCP_PROCSTAT; /* GLCP IO DELAY CONTROLS */ |
Nils Jacobs | e98db79 | 2010-11-03 13:21:41 +0000 | [diff] [blame] | 55 | msr.lo = 0x082b5ad68; |
| 56 | msr.hi = 0x080ad6b57; /* RGB delay = 0x07 */ |
| 57 | wrmsr(msrnum, msr); |
| 58 | |
| 59 | /* Set up DF to output diag information on DF pins. */ |
Ronald G. Minnich | d3ba4aa | 2006-05-02 03:07:11 +0000 | [diff] [blame] | 60 | msrnum = DF_GLD_MSR_MASTER_CONF; |
| 61 | msr.lo = 0x0220; |
| 62 | msr.hi = 0; |
| 63 | wrmsr(msrnum, msr); |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 64 | |
Nils Jacobs | 3344743 | 2010-12-26 05:16:47 +0000 | [diff] [blame] | 65 | msrnum = GLCP_DBGOUT; /* GLCP_DBGOUT MSR */ |
Ronald G. Minnich | d3ba4aa | 2006-05-02 03:07:11 +0000 | [diff] [blame] | 66 | msr.hi = 0x0; |
Nils Jacobs | e98db79 | 2010-11-03 13:21:41 +0000 | [diff] [blame] | 67 | msr.lo = 0x0; /* reset value (SCOPE_SEL = 0) causes FIFO to shift out, */ |
Ronald G. Minnich | d3ba4aa | 2006-05-02 03:07:11 +0000 | [diff] [blame] | 68 | wrmsr(msrnum, msr); |
| 69 | /* end of code for BTM */ |
Ronald G. Minnich | 526b2c4 | 2006-04-10 16:14:19 +0000 | [diff] [blame] | 70 | } |
| 71 | |
Nils Jacobs | e98db79 | 2010-11-03 13:21:41 +0000 | [diff] [blame] | 72 | /* Enable Suspend on Halt */ |
Ronald G. Minnich | 526b2c4 | 2006-04-10 16:14:19 +0000 | [diff] [blame] | 73 | msrnum = CPU_XC_CONFIG; |
| 74 | msr = rdmsr(msrnum); |
| 75 | msr.lo |= XC_CONFIG_SUSP_ON_HLT; |
| 76 | wrmsr(msrnum, msr); |
| 77 | |
Nils Jacobs | e98db79 | 2010-11-03 13:21:41 +0000 | [diff] [blame] | 78 | /* ENable SUSP and allow TSC to run in Suspend */ |
| 79 | /* to keep speed detection happy */ |
Ronald G. Minnich | 526b2c4 | 2006-04-10 16:14:19 +0000 | [diff] [blame] | 80 | msrnum = CPU_BC_CONF_0; |
| 81 | msr = rdmsr(msrnum); |
| 82 | msr.lo |= TSC_SUSP_SET | SUSP_EN_SET; |
| 83 | wrmsr(msrnum, msr); |
| 84 | |
Nils Jacobs | e98db79 | 2010-11-03 13:21:41 +0000 | [diff] [blame] | 85 | /* Setup throttling to proper mode if it is ever enabled. */ |
Nils Jacobs | 3344743 | 2010-12-26 05:16:47 +0000 | [diff] [blame] | 86 | msrnum = GLCP_TH_OD; |
Ronald G. Minnich | 526b2c4 | 2006-04-10 16:14:19 +0000 | [diff] [blame] | 87 | msr.hi = 0x000000000; |
| 88 | msr.lo = 0x00000603C; |
| 89 | wrmsr(msrnum, msr); |
| 90 | |
Nils Jacobs | e98db79 | 2010-11-03 13:21:41 +0000 | [diff] [blame] | 91 | /* FooGlue Setup */ |
Nils Jacobs | 8098e42 | 2010-12-30 19:23:29 +0000 | [diff] [blame] | 92 | /* Set CS5535/CS5536 mode in FooGlue */ |
| 93 | msrnum = FG_GIO_MSR_SEL; |
Ronald G. Minnich | 526b2c4 | 2006-04-10 16:14:19 +0000 | [diff] [blame] | 94 | msr = rdmsr(msrnum); |
| 95 | msr.lo &= ~3; |
Nils Jacobs | 8098e42 | 2010-12-30 19:23:29 +0000 | [diff] [blame] | 96 | msr.lo |= 2; /* IIOC mode CS5535/CS5536 enable. (according to Jordan Crouse the databook is wrong bits 1:0 have to be 2 instead of 1) */ |
Ronald G. Minnich | 526b2c4 | 2006-04-10 16:14:19 +0000 | [diff] [blame] | 97 | wrmsr(msrnum, msr); |
Ronald G. Minnich | 526b2c4 | 2006-04-10 16:14:19 +0000 | [diff] [blame] | 98 | |
Nils Jacobs | e98db79 | 2010-11-03 13:21:41 +0000 | [diff] [blame] | 99 | /* Disable DOT PLL. Graphics init will enable it if needed. */ |
Ronald G. Minnich | 526b2c4 | 2006-04-10 16:14:19 +0000 | [diff] [blame] | 100 | msrnum = GLCP_DOTPLL; |
| 101 | msr = rdmsr(msrnum); |
| 102 | msr.lo |= DOTPPL_LOWER_PD_SET; |
| 103 | wrmsr(msrnum, msr); |
| 104 | |
Nils Jacobs | e98db79 | 2010-11-03 13:21:41 +0000 | [diff] [blame] | 105 | /* Enable RSDC */ |
Nils Jacobs | 3344743 | 2010-12-26 05:16:47 +0000 | [diff] [blame] | 106 | msrnum = CPU_AC_SMM_CTL; |
Ronald G. Minnich | 526b2c4 | 2006-04-10 16:14:19 +0000 | [diff] [blame] | 107 | msr = rdmsr(msrnum); |
| 108 | msr.lo |= 0x08; |
| 109 | wrmsr(msrnum, msr); |
| 110 | |
Nils Jacobs | e98db79 | 2010-11-03 13:21:41 +0000 | [diff] [blame] | 111 | /* Enable BTB */ |
| 112 | /* I hate to put this check here but it doesn't really work in cpubug.asm */ |
Nils Jacobs | 3344743 | 2010-12-26 05:16:47 +0000 | [diff] [blame] | 113 | msrnum = GLCP_CHIP_REVID; |
Ronald G. Minnich | 526b2c4 | 2006-04-10 16:14:19 +0000 | [diff] [blame] | 114 | msr = rdmsr(msrnum); |
Li-Ta Lo | d8d8fff | 2006-04-13 17:00:38 +0000 | [diff] [blame] | 115 | if (msr.lo >= CPU_REV_2_1){ |
Ronald G. Minnich | 526b2c4 | 2006-04-10 16:14:19 +0000 | [diff] [blame] | 116 | msrnum = CPU_PF_BTB_CONF; |
| 117 | msr = rdmsr(msrnum); |
| 118 | msr.lo |= BTB_ENABLE_SET | RETURN_STACK_ENABLE_SET; |
| 119 | wrmsr(msrnum, msr); |
| 120 | } |
| 121 | |
Martin Roth | 4c3ab73 | 2013-07-08 16:23:54 -0600 | [diff] [blame] | 122 | /* FPU imprecise exceptions bit */ |
Ronald G. Minnich | 526b2c4 | 2006-04-10 16:14:19 +0000 | [diff] [blame] | 123 | { |
| 124 | msrnum = CPU_FPU_MSR_MODE; |
| 125 | msr = rdmsr(msrnum); |
| 126 | msr.lo |= FPU_IE_SET; |
| 127 | wrmsr(msrnum, msr); |
| 128 | } |
Ronald G. Minnich | 526b2c4 | 2006-04-10 16:14:19 +0000 | [diff] [blame] | 129 | } |