blob: 6bf046dedc1bbe1e0bda283983178f6ee97af758 [file] [log] [blame]
Timothy Pearsona2f79d52015-02-16 23:24:26 -06001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
5 * Copyright (C) 2013 Google, Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
Timothy Pearsona2f79d52015-02-16 23:24:26 -060015 */
16#include <stdint.h>
17#include <arch/cpu.h>
18#include <cpu/x86/msr.h>
19#include <timer.h>
20#include <device/pci.h>
21#include <device/pci_ids.h>
22
23#include <northbridge/amd/amdht/AsPsDefs.h>
Stefan Reinauer991f1842015-11-22 23:40:29 +010024#include <cpu/amd/msr.h>
Timothy Pearsona2f79d52015-02-16 23:24:26 -060025
26static struct monotonic_counter {
27 int initialized;
28 uint32_t core_frequency;
29 struct mono_time time;
30 uint64_t last_value;
31} mono_counter;
32
33static inline uint64_t read_counter_msr(void)
34{
35 msr_t counter_msr;
36
37 counter_msr = rdmsr(TSC_MSR);
38
39 return ((uint64_t)counter_msr.hi << 32) | (uint64_t)counter_msr.lo;
40}
41
42static void init_timer(void)
43{
44 uint8_t model;
45 uint32_t cpuid_fms;
46 uint8_t cpufid;
47 uint8_t cpudid;
48 uint8_t boost_capable = 0;
49
50 /* Get CPU model */
51 cpuid_fms = cpuid_eax(0x80000001);
52 model = ((cpuid_fms & 0xf0000) >> 16) | ((cpuid_fms & 0xf0) >> 4);
53
54 /* Get boost capability */
55 if ((model == 0x8) || (model == 0x9)) { /* revision D */
56 boost_capable = (pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x18, 4)), 0x15c) & 0x4) >> 2;
57 }
58
59 /* Set up TSC (BKDG v3.62 section 2.9.4)*/
60 msr_t msr = rdmsr(HWCR_MSR);
61 msr.lo |= 0x1000000;
62 wrmsr(HWCR_MSR, msr);
63
64 /* Get core Pstate 0 frequency in MHz */
65 msr = rdmsr(0xC0010064 + boost_capable);
66 cpufid = (msr.lo & 0x3f);
67 cpudid = (msr.lo & 0x1c0) >> 6;
68 mono_counter.core_frequency = (100 * (cpufid + 0x10)) / (0x01 << cpudid);
69
70 mono_counter.last_value = read_counter_msr();
71 mono_counter.initialized = 1;
72}
73
74void timer_monotonic_get(struct mono_time *mt)
75{
76 uint64_t current_tick;
77 uint32_t usecs_elapsed = 0;
78
79 if (!mono_counter.initialized)
80 init_timer();
81
82 current_tick = read_counter_msr();
83 if (mono_counter.core_frequency != 0)
84 usecs_elapsed = (current_tick - mono_counter.last_value) / mono_counter.core_frequency;
85
86 /* Update current time and tick values only if a full tick occurred. */
87 if (usecs_elapsed) {
88 mono_time_add_usecs(&mono_counter.time, usecs_elapsed);
89 mono_counter.last_value = current_tick;
90 }
91
92 /* Save result. */
93 *mt = mono_counter.time;
94}