Marc Jones | c74e362 | 2008-04-22 23:09:34 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2008 Advanced Micro Devices, Inc. |
Timothy Pearson | 730a043 | 2015-10-16 13:51:51 -0500 | [diff] [blame] | 5 | * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering |
Marc Jones | c74e362 | 2008-04-22 23:09:34 +0000 | [diff] [blame] | 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Marc Jones | c74e362 | 2008-04-22 23:09:34 +0000 | [diff] [blame] | 15 | */ |
| 16 | |
Patrick Georgi | 3d5bb23 | 2010-05-09 21:15:13 +0000 | [diff] [blame] | 17 | #include <northbridge/amd/amdmct/amddefs.h> |
| 18 | #include <cpu/amd/mtrr.h> |
Marc Jones | c74e362 | 2008-04-22 23:09:34 +0000 | [diff] [blame] | 19 | |
| 20 | /* |
| 21 | * Default MSR and errata settings. |
| 22 | */ |
| 23 | static const struct { |
| 24 | u32 msr; |
Timothy Pearson | 730a043 | 2015-10-16 13:51:51 -0500 | [diff] [blame] | 25 | uint64_t revision; |
Marc Jones | c74e362 | 2008-04-22 23:09:34 +0000 | [diff] [blame] | 26 | u32 platform; |
| 27 | u32 data_lo; |
| 28 | u32 data_hi; |
| 29 | u32 mask_lo; |
| 30 | u32 mask_hi; |
| 31 | } fam10_msr_default[] = { |
Timothy Pearson | 730a043 | 2015-10-16 13:51:51 -0500 | [diff] [blame] | 32 | { TOP_MEM2, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL, |
Marc Jones | c74e362 | 2008-04-22 23:09:34 +0000 | [diff] [blame] | 33 | 0x00000000, 0x00000000, |
| 34 | 0xFFFFFFFF, 0xFFFFFFFF }, |
| 35 | |
Timothy Pearson | 730a043 | 2015-10-16 13:51:51 -0500 | [diff] [blame] | 36 | { SYSCFG, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL, |
Marc Jones | c74e362 | 2008-04-22 23:09:34 +0000 | [diff] [blame] | 37 | 3 << 21, 0x00000000, |
| 38 | 3 << 21, 0x00000000 }, /* [MtrrTom2En]=1,[TOM2EnWB] = 1*/ |
| 39 | |
Timothy Pearson | 730a043 | 2015-10-16 13:51:51 -0500 | [diff] [blame] | 40 | { MC1_CTL_MASK, AMD_OR_B2, AMD_PTYPE_ALL, |
| 41 | 1 << 18, 0x00000000, |
| 42 | 1 << 18, 0x00000000 }, /* Erratum 586: [DEIBP]=1 */ |
Marc Jones | c74e362 | 2008-04-22 23:09:34 +0000 | [diff] [blame] | 43 | |
Timothy Pearson | 730a043 | 2015-10-16 13:51:51 -0500 | [diff] [blame] | 44 | { MC1_CTL_MASK, AMD_OR_B2, AMD_PTYPE_ALL, |
| 45 | 1 << 15, 0x00000000, |
| 46 | 1 << 15, 0x00000000 }, /* Erratum 593: [BSRP]=1 */ |
| 47 | |
| 48 | { MC1_CTL_MASK, AMD_OR_C0, AMD_PTYPE_ALL, |
| 49 | 1 << 15, 0x00000000, |
| 50 | 1 << 15, 0x00000000 }, /* Erratum 739: [BSRP]=1 */ |
| 51 | |
| 52 | { 0xc0011000, AMD_FAM15_ALL, AMD_PTYPE_ALL, |
| 53 | 1 << 16, 0x00000000, |
| 54 | 1 << 16, 0x00000000 }, /* Erratum 608: [bit 16]=1 */ |
| 55 | |
| 56 | { 0xc0011000, AMD_OR_C0, AMD_PTYPE_ALL, |
| 57 | 1 << 15, 0x00000000, |
| 58 | 1 << 15, 0x00000000 }, /* Erratum 727: [bit 15]=1 */ |
| 59 | |
| 60 | { MC4_CTL_MASK, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL, |
Marc Jones | c74e362 | 2008-04-22 23:09:34 +0000 | [diff] [blame] | 61 | 0xF << 19, 0x00000000, |
| 62 | 0xF << 19, 0x00000000 }, /* [RtryHt[0..3]]=1 */ |
| 63 | |
Timothy Pearson | 730a043 | 2015-10-16 13:51:51 -0500 | [diff] [blame] | 64 | { MC4_CTL_MASK, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL, |
| 65 | 1 << 10, 0x00000000, |
| 66 | 1 << 10, 0x00000000 }, /* [GartTblWkEn]=1 */ |
| 67 | |
Marc Jones | 99fd2a3 | 2009-05-14 23:42:41 +0000 | [diff] [blame] | 68 | { DC_CFG, AMD_FAM10_ALL, AMD_PTYPE_SVR, |
Marc Jones | c74e362 | 2008-04-22 23:09:34 +0000 | [diff] [blame] | 69 | 0x00000000, 0x00000004, |
Timothy Pearson | 730a043 | 2015-10-16 13:51:51 -0500 | [diff] [blame] | 70 | 0x00000000, 0x0000000C }, /* Family 10h: [REQ_CTR] = 1 for Server */ |
Marc Jones | c74e362 | 2008-04-22 23:09:34 +0000 | [diff] [blame] | 71 | |
| 72 | { DC_CFG, AMD_DR_Bx, AMD_PTYPE_SVR, |
| 73 | 0x00000000, 0x00000000, |
Martin Roth | 4c3ab73 | 2013-07-08 16:23:54 -0600 | [diff] [blame] | 74 | 0x00000000, 0x00000C00 }, /* Erratum 326 */ |
Marc Jones | c74e362 | 2008-04-22 23:09:34 +0000 | [diff] [blame] | 75 | |
Timothy Pearson | 730a043 | 2015-10-16 13:51:51 -0500 | [diff] [blame] | 76 | { NB_CFG, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_DC | AMD_PTYPE_MC, |
Marc Jones | c74e362 | 2008-04-22 23:09:34 +0000 | [diff] [blame] | 77 | 0x00000000, 1 << 22, |
| 78 | 0x00000000, 1 << 22 }, /* [ApicInitIDLo]=1 */ |
| 79 | |
Timothy Pearson | 730a043 | 2015-10-16 13:51:51 -0500 | [diff] [blame] | 80 | { NB_CFG, AMD_FAM15_ALL, AMD_PTYPE_DC | AMD_PTYPE_MC, |
| 81 | 1 << 23, 0x00000000, |
| 82 | 1 << 23, 0x00000000 }, /* Erratum 663: [bit 23]=1 */ |
| 83 | |
Marc Jones | c74e362 | 2008-04-22 23:09:34 +0000 | [diff] [blame] | 84 | { BU_CFG2, AMD_DR_Bx, AMD_PTYPE_ALL, |
| 85 | 1 << 29, 0x00000000, |
| 86 | 1 << 29, 0x00000000 }, /* For Bx Smash1GPages=1 */ |
| 87 | |
Marc Jones | 99fd2a3 | 2009-05-14 23:42:41 +0000 | [diff] [blame] | 88 | { DC_CFG, AMD_FAM10_ALL, AMD_PTYPE_ALL, |
Marc Jones | c74e362 | 2008-04-22 23:09:34 +0000 | [diff] [blame] | 89 | 1 << 24, 0x00000000, |
Marc Jones | 35b5361 | 2008-07-23 21:44:23 +0000 | [diff] [blame] | 90 | 1 << 24, 0x00000000 }, /* Erratum #261 [DIS_PIGGY_BACK_SCRUB]=1 */ |
Marc Jones | c74e362 | 2008-04-22 23:09:34 +0000 | [diff] [blame] | 91 | |
Xavi Drudis Ferran | 0e5d3e1 | 2011-02-28 00:18:43 +0000 | [diff] [blame] | 92 | { LS_CFG, AMD_DR_GT_B0, AMD_PTYPE_ALL, |
Marc Jones | c74e362 | 2008-04-22 23:09:34 +0000 | [diff] [blame] | 93 | 0 << 1, 0x00000000, |
| 94 | 1 << 1, 0x00000000 }, /* IDX_MATCH_ALL=0 */ |
| 95 | |
Timothy Pearson | 730a043 | 2015-10-16 13:51:51 -0500 | [diff] [blame] | 96 | { IC_CFG, AMD_OR_C0, AMD_PTYPE_ALL, |
| 97 | 0x00000000, 1 << (39-32), |
| 98 | 0x00000000, 1 << (39-32)}, /* C0 or above [DisLoopPredictor]=1 */ |
| 99 | |
| 100 | { IC_CFG, AMD_OR_C0, AMD_PTYPE_ALL, |
| 101 | 0xf << 1, 0x00000000, |
| 102 | 0xf << 1, 0x00000000}, /* C0 or above [DisIcWayFilter]=0xf */ |
| 103 | |
Marc Jones | 99fd2a3 | 2009-05-14 23:42:41 +0000 | [diff] [blame] | 104 | { BU_CFG, AMD_DR_LT_B3, AMD_PTYPE_ALL, |
Marc Jones | c74e362 | 2008-04-22 23:09:34 +0000 | [diff] [blame] | 105 | 1 << 21, 0x00000000, |
| 106 | 1 << 21, 0x00000000 }, /* Erratum #254 DR B1 BU_CFG[21]=1 */ |
| 107 | |
| 108 | { BU_CFG, AMD_DR_LT_B3, AMD_PTYPE_ALL, |
| 109 | 1 << 23, 0x00000000, |
| 110 | 1 << 23, 0x00000000 }, /* Erratum #309 BU_CFG[23]=1 */ |
| 111 | |
Timothy Pearson | 730a043 | 2015-10-16 13:51:51 -0500 | [diff] [blame] | 112 | { BU_CFG, AMD_FAM15_ALL, AMD_PTYPE_ALL, |
| 113 | 0 << 10, 0x00000000, |
| 114 | 1 << 10, 0x00000000 }, /* [DcacheAgressivePriority]=0 */ |
| 115 | |
Marc Jones | c74e362 | 2008-04-22 23:09:34 +0000 | [diff] [blame] | 116 | /* CPUID_EXT_FEATURES */ |
Timothy Pearson | 730a043 | 2015-10-16 13:51:51 -0500 | [diff] [blame] | 117 | { CPUIDFEATURES, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_DC | AMD_PTYPE_MC, |
Marc Jones | c74e362 | 2008-04-22 23:09:34 +0000 | [diff] [blame] | 118 | 1 << 28, 0x00000000, |
| 119 | 1 << 28, 0x00000000 }, /* [HyperThreadFeatEn]=1 */ |
| 120 | |
Timothy Pearson | 730a043 | 2015-10-16 13:51:51 -0500 | [diff] [blame] | 121 | { CPUIDFEATURES, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_DC, |
Marc Jones | c74e362 | 2008-04-22 23:09:34 +0000 | [diff] [blame] | 122 | 0x00000000, 1 << (33-32), |
| 123 | 0x00000000, 1 << (33-32) }, /* [ExtendedFeatEn]=1 */ |
Xavi Drudis Ferran | e9f0dfe | 2010-08-22 19:49:46 +0000 | [diff] [blame] | 124 | |
Timothy Pearson | 730a043 | 2015-10-16 13:51:51 -0500 | [diff] [blame] | 125 | { DE_CFG, AMD_OR_B2, AMD_PTYPE_ALL, |
| 126 | 1 << 10, 0x00000000, |
| 127 | 1 << 10, 0x00000000 }, /* Bx [ResyncPredSingleDispDis]=1 */ |
| 128 | |
Zheng Bao | 2ca2f17 | 2011-03-28 04:29:14 +0000 | [diff] [blame] | 129 | { BU_CFG2, AMD_DRBH_Cx, AMD_PTYPE_ALL, |
Xavi Drudis Ferran | e9f0dfe | 2010-08-22 19:49:46 +0000 | [diff] [blame] | 130 | 0x00000000, 1 << (35-32), |
Stefan Reinauer | 5ff7c13 | 2011-10-31 12:56:45 -0700 | [diff] [blame] | 131 | 0x00000000, 1 << (35-32) }, /* Erratum 343 (set to 0 after CAR, in post_cache_as_ram()/model_10xxx_init() ) */ |
Zheng Bao | 2ca2f17 | 2011-03-28 04:29:14 +0000 | [diff] [blame] | 132 | |
Timothy Pearson | 730a043 | 2015-10-16 13:51:51 -0500 | [diff] [blame] | 133 | { BU_CFG3, AMD_OR_B2, AMD_PTYPE_ALL, |
| 134 | 0x00000000, 1 << (42-32), |
| 135 | 0x00000000, 1 << (42-32)}, /* Bx [PwcDisableWalkerSharing]=1 */ |
| 136 | |
| 137 | { BU_CFG3, AMD_OR_C0, AMD_PTYPE_ALL, |
Timothy Pearson | 68130f5 | 2015-08-09 02:47:51 -0500 | [diff] [blame] | 138 | 1 << 22, 0x00000000, |
| 139 | 1 << 22, 0x00000000}, /* C0 or above [PfcDoubleStride]=1 */ |
Timothy Pearson | 730a043 | 2015-10-16 13:51:51 -0500 | [diff] [blame] | 140 | |
| 141 | { EX_CFG, AMD_OR_C0, AMD_PTYPE_ALL, |
| 142 | 0x00000000, 1 << (54-32), |
| 143 | 0x00000000, 1 << (54-32)}, /* C0 or above [LateSbzResync]=1 */ |
| 144 | |
| 145 | { LS_CFG2, AMD_OR_C0, AMD_PTYPE_ALL, |
| 146 | 1 << 23, 0x00000000, |
| 147 | 1 << 23, 0x00000000}, /* C0 or above [DisScbThreshold]=1 */ |
| 148 | |
| 149 | { LS_CFG2, AMD_OR_C0, AMD_PTYPE_ALL, |
| 150 | 1 << 14, 0x00000000, |
| 151 | 1 << 14, 0x00000000}, /* C0 or above [ForceSmcCheckFlowStDis]=1 */ |
| 152 | |
| 153 | { LS_CFG2, AMD_OR_C0, AMD_PTYPE_ALL, |
| 154 | 1 << 12, 0x00000000, |
| 155 | 1 << 12, 0x00000000}, /* C0 or above [ForceBusLockDis]=1 */ |
| 156 | |
Zheng Bao | 2ca2f17 | 2011-03-28 04:29:14 +0000 | [diff] [blame] | 157 | { OSVW_ID_Length, AMD_DR_Bx | AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, |
| 158 | 0x00000004, 0x00000000, |
| 159 | 0x00000004, 0x00000000}, /* B0 or Above, OSVW_ID_Length is 0004h */ |
| 160 | |
| 161 | { OSVW_Status, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_MC, |
| 162 | 0x0000000C, 0x00000000, |
| 163 | 0x0000000C, 0x00000000}, /* Cx and Dx multiple-link processor */ |
| 164 | |
Timothy Pearson | 16a3a75 | 2015-09-03 17:43:52 -0500 | [diff] [blame] | 165 | { OSVW_ID_Length, AMD_FAM15_ALL, AMD_PTYPE_ALL, |
| 166 | 0x00000005, 0x00000000, |
| 167 | 0x0000ffff, 0x00000000}, /* OSVW_ID_Length = 0x5 */ |
| 168 | |
| 169 | { OSVW_Status, AMD_FAM15_ALL, AMD_PTYPE_ALL, |
| 170 | 0x00000010, 0x00000000, |
| 171 | 0xffffffff, 0x00000000}, /* OsvwId4 = 0x1 */ |
| 172 | |
Zheng Bao | 2ca2f17 | 2011-03-28 04:29:14 +0000 | [diff] [blame] | 173 | { BU_CFG2, AMD_DR_Dx, AMD_PTYPE_ALL, |
| 174 | 0x00000000, 1 << (50-32), |
| 175 | 0x00000000, 1 << (50-32)}, /* D0 or Above, RdMmExtCfgQwEn*/ |
| 176 | |
Timothy Pearson | 730a043 | 2015-10-16 13:51:51 -0500 | [diff] [blame] | 177 | { BU_CFG2, AMD_FAM15_ALL, AMD_PTYPE_ALL, |
| 178 | 0x00000000, 0x0 << (36-32), |
| 179 | 0x00000000, 0x3 << (36-32)}, /* [ThrottleNbInterface]=0 */ |
| 180 | |
| 181 | { BU_CFG2, AMD_FAM15_ALL, AMD_PTYPE_ALL, |
| 182 | 1 << 10, 0x00000000, |
| 183 | 1 << 10, 0x00000000}, /* [VicResyncChkEn]=1 */ |
| 184 | |
| 185 | { BU_CFG2, AMD_FAM15_ALL, AMD_PTYPE_ALL, |
| 186 | 1 << 11, 0x00000000, |
| 187 | 1 << 11, 0x00000000}, /* Erratum 503: [bit 11]=1 */ |
| 188 | |
Zheng Bao | 2ca2f17 | 2011-03-28 04:29:14 +0000 | [diff] [blame] | 189 | { CPU_ID_EXT_FEATURES_MSR, AMD_DR_Dx, AMD_PTYPE_ALL, |
| 190 | 0x00000000, 1 << (51 - 32), |
| 191 | 0x00000000, 1 << (51 - 32)}, /* G34_PKG | C32_PKG | S1G4_PKG | ASB2_PKG */ |
Timothy Pearson | 730a043 | 2015-10-16 13:51:51 -0500 | [diff] [blame] | 192 | |
| 193 | { CPU_ID_EXT_FEATURES_MSR, AMD_FAM15_ALL, AMD_PTYPE_ALL, |
| 194 | 0x00000000, 1 << (56 - 32), |
| 195 | 0x00000000, 1 << (56 - 32)}, /* [PerfCtrExtNB]=1 */ |
| 196 | |
| 197 | { CPU_ID_EXT_FEATURES_MSR, AMD_FAM15_ALL, AMD_PTYPE_ALL, |
| 198 | 0x00000000, 1 << (55 - 32), |
| 199 | 0x00000000, 1 << (55 - 32)}, /* [PerfCtrExtCore]=1 */ |
| 200 | |
| 201 | { IBS_OP_DATA3, AMD_FAM15_ALL, AMD_PTYPE_ALL, |
| 202 | 0 << 16, 0x00000000, |
| 203 | 1 << 16, 0x00000000}, /* [IbsDcMabHit]=0 */ |
| 204 | |
| 205 | { MC4_MISC0, AMD_FAM15_ALL, AMD_PTYPE_ALL, |
| 206 | 0x00000000, 0x1 << (52-32), |
| 207 | 0x00000000, 0xf << (52-32)}, /* [LvtOffset]=1 */ |
| 208 | |
| 209 | { MC4_MISC1, AMD_FAM15_ALL, AMD_PTYPE_ALL, |
| 210 | 0x00000000, 0x1 << (52-32), |
| 211 | 0x00000000, 0xf << (52-32)}, /* [LvtOffset]=1 */ |
| 212 | |
| 213 | { MC4_MISC2, AMD_FAM15_ALL, AMD_PTYPE_ALL, |
| 214 | 0x00000000, 0x1 << (52-32), |
| 215 | 0x00000000, 0xf << (52-32)}, /* [LvtOffset]=1 */ |
Marc Jones | c74e362 | 2008-04-22 23:09:34 +0000 | [diff] [blame] | 216 | }; |
| 217 | |
| 218 | |
| 219 | /* |
| 220 | * Default PCI and errata settings. |
| 221 | */ |
| 222 | static const struct { |
| 223 | u8 function; |
| 224 | u16 offset; |
Timothy Pearson | 730a043 | 2015-10-16 13:51:51 -0500 | [diff] [blame] | 225 | uint64_t revision; |
Marc Jones | c74e362 | 2008-04-22 23:09:34 +0000 | [diff] [blame] | 226 | u32 platform; |
| 227 | u32 data; |
| 228 | u32 mask; |
| 229 | } fam10_pci_default[] = { |
| 230 | |
| 231 | /* Function 0 - HT Config */ |
Timothy Pearson | 730a043 | 2015-10-16 13:51:51 -0500 | [diff] [blame] | 232 | { 0, 0x68, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL, |
| 233 | 0x000e0000, 0x000e0000 }, /* [19:17] for 8bit APIC config */ |
Marc Jones | c74e362 | 2008-04-22 23:09:34 +0000 | [diff] [blame] | 234 | |
Timothy Pearson | 730a043 | 2015-10-16 13:51:51 -0500 | [diff] [blame] | 235 | { 0, 0x68, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL, |
| 236 | 0x00400000, 0x00600000 }, /* [22:21] DsNpReqLmt = 10b */ |
| 237 | |
| 238 | { 0, 0x68, AMD_FAM10_LT_D, AMD_PTYPE_ALL, |
| 239 | 0x00004000, 0x00006000 }, /* [14:13] BufRelPri = 2h */ |
| 240 | |
| 241 | { 0, 0x68, (AMD_FAM10_REV_D | AMD_FAM15_ALL), AMD_PTYPE_ALL, |
| 242 | 0x00002000, 0x00006000 }, /* [14:13] BufRelPri = 1h */ |
| 243 | |
| 244 | { 0, 0x68, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL, |
| 245 | 0x00000800, 0x00000800 }, /* [11] RspPassPW = 1 */ |
Marc Jones | c74e362 | 2008-04-22 23:09:34 +0000 | [diff] [blame] | 246 | |
| 247 | /* Errata 281 Workaround */ |
| 248 | { 0, 0x68, (AMD_DR_B0 | AMD_DR_B1), |
| 249 | AMD_PTYPE_SVR, 0x00200000, 0x00600000 }, /* [22:21] DsNpReqLmt0 = 01b */ |
| 250 | |
Timothy Pearson | 0122afb | 2015-07-30 14:07:15 -0500 | [diff] [blame] | 251 | { 0, 0x84, AMD_FAM10_ALL, AMD_PTYPE_ALL, |
Marc Jones | c74e362 | 2008-04-22 23:09:34 +0000 | [diff] [blame] | 252 | 0x00002000, 0x00002000 }, /* [13] LdtStopTriEn = 1 */ |
| 253 | |
Timothy Pearson | 0122afb | 2015-07-30 14:07:15 -0500 | [diff] [blame] | 254 | { 0, 0xA4, AMD_FAM10_ALL, AMD_PTYPE_ALL, |
Marc Jones | c74e362 | 2008-04-22 23:09:34 +0000 | [diff] [blame] | 255 | 0x00002000, 0x00002000 }, /* [13] LdtStopTriEn = 1 */ |
| 256 | |
Timothy Pearson | 0122afb | 2015-07-30 14:07:15 -0500 | [diff] [blame] | 257 | { 0, 0xC4, AMD_FAM10_ALL, AMD_PTYPE_ALL, |
Marc Jones | c74e362 | 2008-04-22 23:09:34 +0000 | [diff] [blame] | 258 | 0x00002000, 0x00002000 }, /* [13] LdtStopTriEn = 1 */ |
| 259 | |
Timothy Pearson | 0122afb | 2015-07-30 14:07:15 -0500 | [diff] [blame] | 260 | { 0, 0xE4, AMD_FAM10_ALL, AMD_PTYPE_ALL, |
Marc Jones | c74e362 | 2008-04-22 23:09:34 +0000 | [diff] [blame] | 261 | 0x00002000, 0x00002000 }, /* [13] LdtStopTriEn = 1 */ |
| 262 | |
Timothy Pearson | 0122afb | 2015-07-30 14:07:15 -0500 | [diff] [blame] | 263 | /* FIXME |
| 264 | * Non-C32 packages only |
| 265 | */ |
| 266 | { 0, 0x84, AMD_FAM15_ALL, AMD_PTYPE_ALL, |
| 267 | 0x00000000, 0x00002000 }, /* [13] LdtStopTriEn = 1 */ |
| 268 | |
| 269 | { 0, 0xA4, AMD_FAM15_ALL, AMD_PTYPE_ALL, |
| 270 | 0x00000000, 0x00002000 }, /* [13] LdtStopTriEn = 1 */ |
| 271 | |
| 272 | { 0, 0xC4, AMD_FAM15_ALL, AMD_PTYPE_ALL, |
| 273 | 0x00000000, 0x00002000 }, /* [13] LdtStopTriEn = 1 */ |
| 274 | |
| 275 | { 0, 0xE4, AMD_FAM15_ALL, AMD_PTYPE_ALL, |
| 276 | 0x00000000, 0x00002000 }, /* [13] LdtStopTriEn = 1 */ |
| 277 | |
| 278 | /* FIXME |
| 279 | * C32 package is not supported at this time |
| 280 | */ |
| 281 | |
Marc Jones | aac8dc8 | 2009-06-17 15:33:57 +0000 | [diff] [blame] | 282 | /* Link Global Retry Control Register */ |
Timothy Pearson | 730a043 | 2015-10-16 13:51:51 -0500 | [diff] [blame] | 283 | { 0, 0x150, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL, |
Timothy Pearson | 7c55f37 | 2015-08-02 21:36:24 -0500 | [diff] [blame] | 284 | 0x00073900, 0x00073f70 }, /* TotalRetryAttempts = 0x7, |
| 285 | HtRetryCrcDatInsDynEn = 0x1, |
| 286 | HtRetryCrcCmdPackDynEn = 0x1, |
| 287 | HtRetryCrcDatIns = 0x4, |
| 288 | HtRetryCrcCmdPack = 0x1, |
| 289 | ForceErrType = 0x0, |
| 290 | MultRetryErr = 0x0 */ |
Marc Jones | aac8dc8 | 2009-06-17 15:33:57 +0000 | [diff] [blame] | 291 | |
| 292 | /* Errata 351 |
| 293 | * System software should program the Link Extended Control Registers[LS2En] |
| 294 | * (F0x[18C:170][8]) to 0b for all links. System software should also |
| 295 | * program Link Global Extended Control Register[ForceFullT0] |
| 296 | * (F0x16C[15:13]) to 000b */ |
| 297 | |
Zheng Bao | 2ca2f17 | 2011-03-28 04:29:14 +0000 | [diff] [blame] | 298 | { 0, 0x170, AMD_FAM10_ALL, AMD_PTYPE_ALL, /* Fix FAM10_ALL when fixed in rev guide */ |
Marc Jones | aac8dc8 | 2009-06-17 15:33:57 +0000 | [diff] [blame] | 299 | 0x00000000, 0x00000100 }, |
Zheng Bao | 2ca2f17 | 2011-03-28 04:29:14 +0000 | [diff] [blame] | 300 | { 0, 0x174, AMD_FAM10_ALL, AMD_PTYPE_ALL, |
Marc Jones | aac8dc8 | 2009-06-17 15:33:57 +0000 | [diff] [blame] | 301 | 0x00000000, 0x00000100 }, |
Zheng Bao | 2ca2f17 | 2011-03-28 04:29:14 +0000 | [diff] [blame] | 302 | { 0, 0x178, AMD_FAM10_ALL, AMD_PTYPE_ALL, |
Marc Jones | aac8dc8 | 2009-06-17 15:33:57 +0000 | [diff] [blame] | 303 | 0x00000000, 0x00000100 }, |
Zheng Bao | 2ca2f17 | 2011-03-28 04:29:14 +0000 | [diff] [blame] | 304 | { 0, 0x17C, AMD_FAM10_ALL, AMD_PTYPE_ALL, |
Marc Jones | aac8dc8 | 2009-06-17 15:33:57 +0000 | [diff] [blame] | 305 | 0x00000000, 0x00000100 }, |
Zheng Bao | 2ca2f17 | 2011-03-28 04:29:14 +0000 | [diff] [blame] | 306 | { 0, 0x180, AMD_FAM10_ALL, AMD_PTYPE_ALL, |
Marc Jones | aac8dc8 | 2009-06-17 15:33:57 +0000 | [diff] [blame] | 307 | 0x00000000, 0x00000100 }, |
Zheng Bao | 2ca2f17 | 2011-03-28 04:29:14 +0000 | [diff] [blame] | 308 | { 0, 0x184, AMD_FAM10_ALL, AMD_PTYPE_ALL, |
Marc Jones | aac8dc8 | 2009-06-17 15:33:57 +0000 | [diff] [blame] | 309 | 0x00000000, 0x00000100 }, |
Zheng Bao | 2ca2f17 | 2011-03-28 04:29:14 +0000 | [diff] [blame] | 310 | { 0, 0x188, AMD_FAM10_ALL, AMD_PTYPE_ALL, |
Marc Jones | aac8dc8 | 2009-06-17 15:33:57 +0000 | [diff] [blame] | 311 | 0x00000000, 0x00000100 }, |
Zheng Bao | 2ca2f17 | 2011-03-28 04:29:14 +0000 | [diff] [blame] | 312 | { 0, 0x18C, AMD_FAM10_ALL, AMD_PTYPE_ALL, |
Marc Jones | aac8dc8 | 2009-06-17 15:33:57 +0000 | [diff] [blame] | 313 | 0x00000000, 0x00000100 }, |
Marc Jones | aac8dc8 | 2009-06-17 15:33:57 +0000 | [diff] [blame] | 314 | |
Marc Jones | c74e362 | 2008-04-22 23:09:34 +0000 | [diff] [blame] | 315 | /* Link Global Extended Control Register */ |
Zheng Bao | 2ca2f17 | 2011-03-28 04:29:14 +0000 | [diff] [blame] | 316 | { 0, 0x16C, AMD_FAM10_ALL, AMD_PTYPE_ALL, |
| 317 | 0x00000014, 0x0000003F }, /* [15:13] ForceFullT0 = 0b, |
Timothy Pearson | 730a043 | 2015-10-16 13:51:51 -0500 | [diff] [blame] | 318 | * Set T0Time 14h per BKDG */ |
| 319 | |
| 320 | { 0, 0x170, AMD_FAM15_ALL, AMD_PTYPE_ALL, |
| 321 | 0x00000100, 0x00000100 }, |
| 322 | { 0, 0x174, AMD_FAM15_ALL, AMD_PTYPE_ALL, |
| 323 | 0x00000100, 0x00000100 }, |
| 324 | { 0, 0x178, AMD_FAM15_ALL, AMD_PTYPE_ALL, |
| 325 | 0x00000100, 0x00000100 }, |
| 326 | { 0, 0x17C, AMD_FAM15_ALL, AMD_PTYPE_ALL, |
| 327 | 0x00000100, 0x00000100 }, |
| 328 | { 0, 0x180, AMD_FAM15_ALL, AMD_PTYPE_ALL, |
| 329 | 0x00000100, 0x00000100 }, |
| 330 | { 0, 0x184, AMD_FAM15_ALL, AMD_PTYPE_ALL, |
| 331 | 0x00000100, 0x00000100 }, |
| 332 | { 0, 0x188, AMD_FAM15_ALL, AMD_PTYPE_ALL, |
| 333 | 0x00000100, 0x00000100 }, |
| 334 | { 0, 0x18C, AMD_FAM15_ALL, AMD_PTYPE_ALL, |
| 335 | 0x00000100, 0x00000100 }, |
| 336 | |
| 337 | /* Link Global Extended Control Register */ |
| 338 | { 0, 0x16C, AMD_FAM15_ALL, AMD_PTYPE_ALL, |
| 339 | 0x00000014, 0x0000003F }, /* [15:13] ForceFullT0 = 111b, |
| 340 | * Set T0Time 26h per BKDG */ |
| 341 | |
| 342 | { 0, 0x16C, AMD_FAM15_ALL, AMD_PTYPE_ALL, |
| 343 | 0x7 << 13, 0x7 << 13 }, /* [15:13] ForceFullT0 = 7h */ |
| 344 | |
| 345 | { 0, 0x16C, AMD_FAM15_ALL, AMD_PTYPE_ALL, |
| 346 | 0x26, 0x3f }, /* [5:0] T0Time = 26h */ |
Marc Jones | aac8dc8 | 2009-06-17 15:33:57 +0000 | [diff] [blame] | 347 | |
Marc Jones | c74e362 | 2008-04-22 23:09:34 +0000 | [diff] [blame] | 348 | |
| 349 | /* Function 1 - Map Init */ |
| 350 | |
| 351 | /* Before reading F1x114_x2 or F1x114_x3 software must |
| 352 | * initialize the registers or NB Array MCA errors may |
| 353 | * occur. BIOS should initialize index 0h of F1x114_x2 and |
| 354 | * F1x114_x3 to prevent reads from F1x114 from generating NB |
| 355 | * Array MCA errors. BKDG Doc #3116 Rev 1.07 |
| 356 | */ |
| 357 | |
Marc Jones | 99fd2a3 | 2009-05-14 23:42:41 +0000 | [diff] [blame] | 358 | { 1, 0x110, AMD_FAM10_ALL, AMD_PTYPE_ALL, |
Marc Jones | c74e362 | 2008-04-22 23:09:34 +0000 | [diff] [blame] | 359 | 0x20000000, 0xFFFFFFFF }, /* Select extended MMIO Base */ |
| 360 | |
Marc Jones | 99fd2a3 | 2009-05-14 23:42:41 +0000 | [diff] [blame] | 361 | { 1, 0x114, AMD_FAM10_ALL, AMD_PTYPE_ALL, |
Marc Jones | c74e362 | 2008-04-22 23:09:34 +0000 | [diff] [blame] | 362 | 0x00000000, 0xFFFFFFFF }, /* Clear map */ |
| 363 | |
Marc Jones | 99fd2a3 | 2009-05-14 23:42:41 +0000 | [diff] [blame] | 364 | { 1, 0x110, AMD_FAM10_ALL, AMD_PTYPE_ALL, |
Marc Jones | c74e362 | 2008-04-22 23:09:34 +0000 | [diff] [blame] | 365 | 0x30000000, 0xFFFFFFFF }, /* Select extended MMIO Base */ |
| 366 | |
Marc Jones | 99fd2a3 | 2009-05-14 23:42:41 +0000 | [diff] [blame] | 367 | { 1, 0x114, AMD_FAM10_ALL, AMD_PTYPE_ALL, |
Marc Jones | c74e362 | 2008-04-22 23:09:34 +0000 | [diff] [blame] | 368 | 0x00000000, 0xFFFFFFFF }, /* Clear map */ |
| 369 | |
| 370 | /* Function 2 - DRAM Controller */ |
| 371 | |
| 372 | /* Function 3 - Misc. Control */ |
Timothy Pearson | 730a043 | 2015-10-16 13:51:51 -0500 | [diff] [blame] | 373 | { 3, 0x40, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL, |
Marc Jones | c74e362 | 2008-04-22 23:09:34 +0000 | [diff] [blame] | 374 | 0x00000100, 0x00000100 }, /* [8] MstrAbrtEn */ |
| 375 | |
Timothy Pearson | 730a043 | 2015-10-16 13:51:51 -0500 | [diff] [blame] | 376 | { 3, 0x44, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL, |
Marc Jones | 35b5361 | 2008-07-23 21:44:23 +0000 | [diff] [blame] | 377 | 0x4A30005C, 0x4A30005C }, /* [30] SyncOnDramAdrParErrEn = 1, |
| 378 | [27] NbMcaToMstCpuEn = 1, |
| 379 | [25] DisPciCfgCpuErrRsp = 1, |
| 380 | [21] SyncOnAnyErrEn = 1, |
| 381 | [20] SyncOnWDTEn = 1, |
| 382 | [6] CpuErrDis = 1, |
| 383 | [4] SyncPktPropDis = 1, |
| 384 | [3] SyncPktGenDis = 1, |
| 385 | [2] SyncOnUcEccEn = 1 */ |
Marc Jones | c74e362 | 2008-04-22 23:09:34 +0000 | [diff] [blame] | 386 | |
| 387 | /* XBAR buffer settings */ |
Timothy Pearson | 51cfbcd | 2015-08-02 21:18:29 -0500 | [diff] [blame] | 388 | { 3, 0x6c, AMD_FAM10_ALL & ~(AMD_DR_Dx), AMD_PTYPE_ALL, |
| 389 | 0x00018052, 0x700780f7 }, /* IsocRspDBC = 0x0, |
| 390 | UpRspDBC = 0x1, |
| 391 | DatBuf24 = 0x1, |
| 392 | DnRspDBC = 0x1, |
| 393 | DnReqDBC = 0x1, |
| 394 | UpReqDBC = 0x2 */ |
| 395 | |
| 396 | /* XBAR buffer settings */ |
| 397 | { 3, 0x6c, AMD_DR_Dx, AMD_PTYPE_ALL, |
| 398 | 0x00028052, 0x700780f7 }, /* IsocRspDBC = 0x0, |
| 399 | UpRspDBC = 0x2, |
| 400 | DatBuf24 = 0x1, |
| 401 | DnRspDBC = 0x1, |
| 402 | DnReqDBC = 0x1, |
| 403 | UpReqDBC = 0x2 */ |
Timothy Pearson | 730a043 | 2015-10-16 13:51:51 -0500 | [diff] [blame] | 404 | |
| 405 | /* XBAR buffer settings */ |
| 406 | { 3, 0x6c, AMD_FAM15_ALL, AMD_PTYPE_ALL, |
Timothy Pearson | 51cfbcd | 2015-08-02 21:18:29 -0500 | [diff] [blame] | 407 | 0x10010052, 0x700700f7 }, /* IsocRspDBC = 0x1, |
| 408 | UpRspDBC = 0x1, |
| 409 | DnRspDBC = 0x1, |
| 410 | DnReqDBC = 0x1, |
| 411 | UpReqDBC = 0x2 */ |
Marc Jones | c74e362 | 2008-04-22 23:09:34 +0000 | [diff] [blame] | 412 | |
| 413 | /* Errata 281 Workaround */ |
Timothy Pearson | 51cfbcd | 2015-08-02 21:18:29 -0500 | [diff] [blame] | 414 | { 3, 0x6c, (AMD_DR_B0 | AMD_DR_B1), |
Marc Jones | c74e362 | 2008-04-22 23:09:34 +0000 | [diff] [blame] | 415 | AMD_PTYPE_SVR, 0x00010094, 0x700780F7 }, |
| 416 | |
Timothy Pearson | 51cfbcd | 2015-08-02 21:18:29 -0500 | [diff] [blame] | 417 | { 3, 0x6c, AMD_FAM10_ALL, AMD_PTYPE_UMA, |
Marc Jones | c74e362 | 2008-04-22 23:09:34 +0000 | [diff] [blame] | 418 | 0x60018051, 0x700780F7 }, |
| 419 | |
Timothy Pearson | 51cfbcd | 2015-08-02 21:18:29 -0500 | [diff] [blame] | 420 | { 3, 0x70, AMD_FAM10_ALL & ~(AMD_DR_Dx), AMD_PTYPE_ALL, |
| 421 | 0x00041153, 0x777777f7 }, /* IsocRspCBC = 0x0, |
| 422 | IsocPreqCBC = 0x0, |
| 423 | IsocReqCBC = 0x0, |
| 424 | UpRspCBC = 0x4, |
| 425 | DnPreqCBC = 0x1, |
| 426 | UpPreqCBC = 0x1, |
| 427 | DnRspCBC = 0x1, |
| 428 | DnReqCBC = 0x1, |
| 429 | UpReqCBC = 0x3 */ |
| 430 | |
| 431 | { 3, 0x70, AMD_DR_Dx, AMD_PTYPE_ALL, |
| 432 | 0x00051153, 0x777777f7 }, /* IsocRspCBC = 0x0, |
| 433 | IsocPreqCBC = 0x0, |
| 434 | IsocReqCBC = 0x0, |
| 435 | UpRspCBC = 0x5, |
| 436 | DnPreqCBC = 0x1, |
| 437 | UpPreqCBC = 0x1, |
| 438 | DnRspCBC = 0x1, |
| 439 | DnReqCBC = 0x1, |
| 440 | UpReqCBC = 0x3 */ |
Marc Jones | c74e362 | 2008-04-22 23:09:34 +0000 | [diff] [blame] | 441 | |
Timothy Pearson | 730a043 | 2015-10-16 13:51:51 -0500 | [diff] [blame] | 442 | { 3, 0x70, AMD_FAM15_ALL, AMD_PTYPE_ALL, |
Timothy Pearson | 51cfbcd | 2015-08-02 21:18:29 -0500 | [diff] [blame] | 443 | 0x10171155, 0x777777f7 }, /* IsocRspCBC = 0x1, |
| 444 | IsocPreqCBC = 0x0, |
| 445 | IsocReqCBC = 0x1, |
| 446 | UpRspCBC = 0x7, |
| 447 | DnPreqCBC = 0x1, |
| 448 | UpPreqCBC = 0x1, |
| 449 | DnRspCBC = 0x1, |
| 450 | DnReqCBC = 0x1, |
| 451 | UpReqCBC = 0x5 */ |
Timothy Pearson | 730a043 | 2015-10-16 13:51:51 -0500 | [diff] [blame] | 452 | |
Marc Jones | 99fd2a3 | 2009-05-14 23:42:41 +0000 | [diff] [blame] | 453 | { 3, 0x70, AMD_FAM10_ALL, AMD_PTYPE_UMA, |
Timothy Pearson | 51cfbcd | 2015-08-02 21:18:29 -0500 | [diff] [blame] | 454 | 0x61221151, 0x777777f7 }, /* IsocRspCBC = 0x6, |
| 455 | IsocPreqCBC = 0x1, |
| 456 | IsocReqCBC = 0x2, |
| 457 | UpRspCBC = 0x2, |
| 458 | DnPreqCBC = 0x1, |
| 459 | UpPreqCBC = 0x1, |
| 460 | DnRspCBC = 0x1, |
| 461 | DnReqCBC = 0x1, |
| 462 | UpReqCBC = 0x1 */ |
| 463 | |
| 464 | { 3, 0x74, AMD_FAM10_ALL, ~AMD_PTYPE_UMA, |
| 465 | 0x00081111, 0xf7ff7777 }, /* DRReqCBC = 0x0, |
| 466 | IsocPreqCBC = 0x0, |
| 467 | IsocReqCBC = 0x0, |
| 468 | ProbeCBC = 0x8, |
| 469 | DnPreqCBC = 0x1, |
| 470 | UpPreqCBC = 0x1, |
| 471 | DnReqCBC = 0x1, |
| 472 | UpReqCBC = 0x1 */ |
Marc Jones | c74e362 | 2008-04-22 23:09:34 +0000 | [diff] [blame] | 473 | |
Marc Jones | 99fd2a3 | 2009-05-14 23:42:41 +0000 | [diff] [blame] | 474 | { 3, 0x74, AMD_FAM10_ALL, AMD_PTYPE_UMA, |
Timothy Pearson | 51cfbcd | 2015-08-02 21:18:29 -0500 | [diff] [blame] | 475 | 0x00480101, 0xf7ff7777 }, /* DRReqCBC = 0x0, |
| 476 | IsocPreqCBC = 0x0, |
| 477 | IsocReqCBC = 0x4, |
| 478 | ProbeCBC = 0x8, |
| 479 | DnPreqCBC = 0x0, |
| 480 | UpPreqCBC = 0x1, |
| 481 | DnReqCBC = 0x0, |
| 482 | UpReqCBC = 0x1 */ |
Marc Jones | c74e362 | 2008-04-22 23:09:34 +0000 | [diff] [blame] | 483 | |
Timothy Pearson | 730a043 | 2015-10-16 13:51:51 -0500 | [diff] [blame] | 484 | { 3, 0x74, AMD_FAM15_ALL, AMD_PTYPE_ALL, |
Timothy Pearson | 51cfbcd | 2015-08-02 21:18:29 -0500 | [diff] [blame] | 485 | 0x00172111, 0xf7ff7777 }, /* DRReqCBC = 0x0, |
| 486 | IsocPreqCBC = 0x0, |
| 487 | IsocReqCBC = 0x1, |
| 488 | ProbeCBC = 0x7, |
| 489 | DnPreqCBC = 0x2, |
| 490 | UpPreqCBC = 0x1, |
| 491 | DnReqCBC = 0x1, |
| 492 | UpReqCBC = 0x1 */ |
Timothy Pearson | 730a043 | 2015-10-16 13:51:51 -0500 | [diff] [blame] | 493 | |
Timothy Pearson | 51cfbcd | 2015-08-02 21:18:29 -0500 | [diff] [blame] | 494 | { 3, 0x7c, AMD_FAM10_ALL & ~(AMD_DR_Dx), AMD_PTYPE_ALL, |
| 495 | 0x00090914, 0x707fff1f }, /* XBar2SriFreeListCBInc = 0x0, |
| 496 | Sri2XbarFreeRspDBC = 0x0, |
| 497 | Sri2XbarFreeXreqDBC = 0x9, |
| 498 | Sri2XbarFreeRspCBC = 0x0, |
| 499 | Sri2XbarFreeXreqCBC = 0x9, |
| 500 | Xbar2SriFreeListCBC = 0x14 */ |
| 501 | |
| 502 | { 3, 0x7c, AMD_DR_Dx, AMD_PTYPE_ALL, |
| 503 | 0x00090a18, 0x707fff1f }, /* XBar2SriFreeListCBInc = 0x0, |
| 504 | Sri2XbarFreeRspDBC = 0x0, |
| 505 | Sri2XbarFreeXreqDBC = 0x9, |
| 506 | Sri2XbarFreeRspCBC = 0x0, |
| 507 | Sri2XbarFreeXreqCBC = 0x9, |
| 508 | Xbar2SriFreeListCBC = 0x14 */ |
Marc Jones | c74e362 | 2008-04-22 23:09:34 +0000 | [diff] [blame] | 509 | |
| 510 | /* Errata 281 Workaround */ |
| 511 | { 3, 0x7C, ( AMD_DR_B0 | AMD_DR_B1), |
| 512 | AMD_PTYPE_SVR, 0x00144514, 0x707FFF1F }, |
| 513 | |
Timothy Pearson | 51cfbcd | 2015-08-02 21:18:29 -0500 | [diff] [blame] | 514 | { 3, 0x7c, AMD_FAM15_ALL, AMD_PTYPE_ALL, |
| 515 | 0x040d0f16, 0x77ffff1f }, /* XBar2SriFreeListCBInc = 0x0, |
| 516 | SrqExtFreeListBC = 0x8, |
| 517 | Sri2XbarFreeRspDBC = 0x0, |
| 518 | Sri2XbarFreeXreqDBC = 0xd, |
| 519 | Sri2XbarFreeRspCBC = 0x0, |
| 520 | Sri2XbarFreeXreqCBC = 0xf, |
| 521 | Xbar2SriFreeListCBC = 0x16 */ |
Timothy Pearson | 730a043 | 2015-10-16 13:51:51 -0500 | [diff] [blame] | 522 | |
Marc Jones | 99fd2a3 | 2009-05-14 23:42:41 +0000 | [diff] [blame] | 523 | { 3, 0x7C, AMD_FAM10_ALL, AMD_PTYPE_UMA, |
Marc Jones | c74e362 | 2008-04-22 23:09:34 +0000 | [diff] [blame] | 524 | 0x00070814, 0x007FFF1F }, |
| 525 | |
Marc Jones | 99fd2a3 | 2009-05-14 23:42:41 +0000 | [diff] [blame] | 526 | { 3, 0x140, AMD_FAM10_ALL, AMD_PTYPE_ALL, |
Marc Jones | c74e362 | 2008-04-22 23:09:34 +0000 | [diff] [blame] | 527 | 0x00800756, 0x00F3FFFF }, |
| 528 | |
Marc Jones | 99fd2a3 | 2009-05-14 23:42:41 +0000 | [diff] [blame] | 529 | { 3, 0x140, AMD_FAM10_ALL, AMD_PTYPE_UMA, |
Marc Jones | c74e362 | 2008-04-22 23:09:34 +0000 | [diff] [blame] | 530 | 0x00C37756, 0x00F3FFFF }, |
| 531 | |
Marc Jones | 99fd2a3 | 2009-05-14 23:42:41 +0000 | [diff] [blame] | 532 | { 3, 0x144, AMD_FAM10_ALL, AMD_PTYPE_UMA, |
Marc Jones | c74e362 | 2008-04-22 23:09:34 +0000 | [diff] [blame] | 533 | 0x00000036, 0x000000FF }, |
| 534 | |
Timothy Pearson | 965704a | 2015-08-07 19:04:49 -0500 | [diff] [blame] | 535 | { 3, 0x140, AMD_FAM15_ALL, AMD_PTYPE_ALL, |
| 536 | 0x00a11755, 0x00f3ffff }, |
| 537 | |
Marc Jones | c74e362 | 2008-04-22 23:09:34 +0000 | [diff] [blame] | 538 | /* Errata 281 Workaround */ |
| 539 | { 3, 0x144, ( AMD_DR_B0 | AMD_DR_B1), |
| 540 | AMD_PTYPE_SVR, 0x00000001, 0x0000000F }, |
| 541 | /* [3:0] RspTok = 0001b */ |
| 542 | |
Timothy Pearson | 730a043 | 2015-10-16 13:51:51 -0500 | [diff] [blame] | 543 | { 3, 0x144, AMD_FAM15_ALL, AMD_PTYPE_ALL, |
| 544 | 0x00000028, 0x000000ff }, |
| 545 | |
Marc Jones | 99fd2a3 | 2009-05-14 23:42:41 +0000 | [diff] [blame] | 546 | { 3, 0x148, AMD_FAM10_ALL, AMD_PTYPE_UMA, |
Marc Jones | c74e362 | 2008-04-22 23:09:34 +0000 | [diff] [blame] | 547 | 0x8000052A, 0xD5FFFFFF }, |
| 548 | |
Timothy Pearson | 965704a | 2015-08-07 19:04:49 -0500 | [diff] [blame] | 549 | /* Core Interface Buffer Count */ |
| 550 | { 3, 0x1a0, AMD_FAM15_ALL, AMD_PTYPE_ALL, |
| 551 | 0x00034004, 0x00037007 }, /* CpuToNbFreeBufCnt = 0x3, |
| 552 | L3ToSriReqCBC = 0x4, |
| 553 | L3FreeListCBC = default, |
| 554 | CpuCmdBufCnt = 0x4 */ |
| 555 | |
Marc Jones | c74e362 | 2008-04-22 23:09:34 +0000 | [diff] [blame] | 556 | /* ACPI Power State Control Reg1 */ |
Marc Jones | 99fd2a3 | 2009-05-14 23:42:41 +0000 | [diff] [blame] | 557 | { 3, 0x80, AMD_FAM10_ALL, AMD_PTYPE_ALL, |
Marc Jones | c74e362 | 2008-04-22 23:09:34 +0000 | [diff] [blame] | 558 | 0xE6002200, 0xFFFFFFFF }, |
| 559 | |
Timothy Pearson | 730a043 | 2015-10-16 13:51:51 -0500 | [diff] [blame] | 560 | /* ACPI Power State Control Reg1 */ |
| 561 | { 3, 0x80, AMD_FAM15_ALL, AMD_PTYPE_ALL, |
| 562 | 0xe20be200, 0xefefef00 }, |
| 563 | |
Marc Jones | c74e362 | 2008-04-22 23:09:34 +0000 | [diff] [blame] | 564 | /* ACPI Power State Control Reg2 */ |
Marc Jones | 99fd2a3 | 2009-05-14 23:42:41 +0000 | [diff] [blame] | 565 | { 3, 0x84, AMD_FAM10_ALL, AMD_PTYPE_ALL, |
Marc Jones | c74e362 | 2008-04-22 23:09:34 +0000 | [diff] [blame] | 566 | 0xA0E641E6, 0xFFFFFFFF }, |
| 567 | |
Timothy Pearson | 730a043 | 2015-10-16 13:51:51 -0500 | [diff] [blame] | 568 | /* ACPI Power State Control Reg2 */ |
| 569 | { 3, 0x84, AMD_FAM15_ALL, AMD_PTYPE_ALL, |
| 570 | 0x01e200e2, 0xefef00ef }, |
| 571 | |
Marc Jones | 99fd2a3 | 2009-05-14 23:42:41 +0000 | [diff] [blame] | 572 | { 3, 0xA0, AMD_FAM10_ALL, AMD_PTYPE_MOB | AMD_PTYPE_DSK, |
Marc Jones | c74e362 | 2008-04-22 23:09:34 +0000 | [diff] [blame] | 573 | 0x00000080, 0x00000080 }, /* [7] PSIVidEnable */ |
| 574 | |
Xavi Drudis Ferran | 0e5d3e1 | 2011-02-28 00:18:43 +0000 | [diff] [blame] | 575 | { 3, 0xA0, AMD_DR_Bx, AMD_PTYPE_ALL, |
| 576 | 0x00002800, 0x000003800 }, /* [13:11] PllLockTime = 5 */ |
| 577 | |
Timothy Pearson | 730a043 | 2015-10-16 13:51:51 -0500 | [diff] [blame] | 578 | { 3, 0xA0, ((AMD_FAM10_ALL | AMD_FAM15_ALL) & ~(AMD_DR_Bx)), AMD_PTYPE_ALL, |
Xavi Drudis Ferran | 0e5d3e1 | 2011-02-28 00:18:43 +0000 | [diff] [blame] | 579 | 0x00000800, 0x000003800 }, /* [13:11] PllLockTime = 1 */ |
Marc Jones | c74e362 | 2008-04-22 23:09:34 +0000 | [diff] [blame] | 580 | |
| 581 | /* Reported Temp Control Register */ |
Timothy Pearson | 730a043 | 2015-10-16 13:51:51 -0500 | [diff] [blame] | 582 | { 3, 0xA4, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL, |
Marc Jones | c74e362 | 2008-04-22 23:09:34 +0000 | [diff] [blame] | 583 | 0x00000080, 0x00000080 }, /* [7] TempSlewDnEn = 1 */ |
| 584 | |
| 585 | /* Clock Power/Timing Control 0 Register */ |
Timothy Pearson | 730a043 | 2015-10-16 13:51:51 -0500 | [diff] [blame] | 586 | { 3, 0xD4, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL, |
Marc Jones | c74e362 | 2008-04-22 23:09:34 +0000 | [diff] [blame] | 587 | 0xC0000F00, 0xF0000F00 }, /* [31] NbClkDivApplyAll = 1, |
| 588 | [30:28] NbClkDiv = 100b,[11:8] ClkRampHystSel = 1111b */ |
| 589 | |
| 590 | /* Clock Power/Timing Control 1 Register */ |
Timothy Pearson | 730a043 | 2015-10-16 13:51:51 -0500 | [diff] [blame] | 591 | { 3, 0xD8, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL, |
| 592 | 0x03000010, 0x0F000070 }, /* [6:4] VSRampTime = 1, |
| 593 | * [27:24] ReConDel = 3 */ |
| 594 | |
| 595 | /* Clock Power/Timing Control 1 Register */ |
Marc Jones | 99fd2a3 | 2009-05-14 23:42:41 +0000 | [diff] [blame] | 596 | { 3, 0xD8, AMD_FAM10_ALL, AMD_PTYPE_ALL, |
Timothy Pearson | 730a043 | 2015-10-16 13:51:51 -0500 | [diff] [blame] | 597 | 0x00000006, 0x00000007 }, /* [2:0] VSSlamTime = 6 */ |
Marc Jones | c74e362 | 2008-04-22 23:09:34 +0000 | [diff] [blame] | 598 | |
| 599 | |
| 600 | /* Clock Power/Timing Control 2 Register */ |
Timothy Pearson | 730a043 | 2015-10-16 13:51:51 -0500 | [diff] [blame] | 601 | { 3, 0xDC, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL, |
Marc Jones | c74e362 | 2008-04-22 23:09:34 +0000 | [diff] [blame] | 602 | 0x00005000, 0x00007000 }, /* [14:12] NbsynPtrAdj = 5 */ |
| 603 | |
| 604 | |
| 605 | /* Extended NB MCA Config Register */ |
Timothy Pearson | 730a043 | 2015-10-16 13:51:51 -0500 | [diff] [blame] | 606 | { 3, 0x180, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL, |
Marc Jones | 35b5361 | 2008-07-23 21:44:23 +0000 | [diff] [blame] | 607 | 0x007003E2, 0x007003E2 }, /* [22:20] = SyncFloodOn_Err = 7, |
| 608 | [9] SyncOnUncNbAryEn = 1 , |
| 609 | [8] SyncOnProtEn = 1, |
| 610 | [7] SyncFloodOnTgtAbtErr = 1, |
| 611 | [6] SyncFloodOnDatErr = 1, |
| 612 | [5] DisPciCfgCpuMstAbtRsp = 1, |
| 613 | [1] SyncFloodOnUsPwDataErr = 1 */ |
Marc Jones | c74e362 | 2008-04-22 23:09:34 +0000 | [diff] [blame] | 614 | |
Timothy Pearson | 99f8042 | 2015-08-07 23:58:28 -0500 | [diff] [blame] | 615 | /* NB Configuration 2 */ |
| 616 | { 3, 0x188, AMD_DR_GT_B0, AMD_PTYPE_ALL, |
| 617 | 0x00000010, 0x00000010 }, /* EnStpGntOnFlushMaskWakeup = 0x1 */ |
| 618 | |
| 619 | /* NB Configuration 2 */ |
| 620 | { 3, 0x188, AMD_FAM15_ALL, AMD_PTYPE_ALL, |
| 621 | 0x00000200, 0x00000200 }, /* DisL3HiPriFreeListAlloc = 0x1 */ |
| 622 | |
Zheng Bao | 2ca2f17 | 2011-03-28 04:29:14 +0000 | [diff] [blame] | 623 | /* errata 346 - Fam10 C2, C3 |
Marc Jones | aac8dc8 | 2009-06-17 15:33:57 +0000 | [diff] [blame] | 624 | * System software should set F3x188[22] to 1b. */ |
Xavi Drudis Ferran | cc6244a | 2010-08-22 19:48:29 +0000 | [diff] [blame] | 625 | { 3, 0x188, AMD_DR_Cx, AMD_PTYPE_ALL, |
Marc Jones | aac8dc8 | 2009-06-17 15:33:57 +0000 | [diff] [blame] | 626 | 0x00400000, 0x00400000 }, |
| 627 | |
Marc Jones | c74e362 | 2008-04-22 23:09:34 +0000 | [diff] [blame] | 628 | /* L3 Control Register */ |
Timothy Pearson | 730a043 | 2015-10-16 13:51:51 -0500 | [diff] [blame] | 629 | { 3, 0x1b8, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL, |
Marc Jones | c74e362 | 2008-04-22 23:09:34 +0000 | [diff] [blame] | 630 | 0x00001000, 0x00001000 }, /* [12] = L3PrivReplEn */ |
| 631 | |
Timothy Pearson | 16a3a75 | 2015-09-03 17:43:52 -0500 | [diff] [blame] | 632 | /* Errata 504 workaround */ |
| 633 | { 3, 0x1b8, AMD_FAM15_ALL, AMD_PTYPE_ALL, |
| 634 | 0x00040000, 0x00040000 }, /* [18] = 1b */ |
| 635 | |
Marc Jones | c74e362 | 2008-04-22 23:09:34 +0000 | [diff] [blame] | 636 | /* IBS Control Register */ |
Timothy Pearson | 730a043 | 2015-10-16 13:51:51 -0500 | [diff] [blame] | 637 | { 3, 0x1cc, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL, |
Marc Jones | c74e362 | 2008-04-22 23:09:34 +0000 | [diff] [blame] | 638 | 0x00000100, 0x00000100 }, /* [8] = LvtOffsetVal */ |
Timothy Pearson | 730a043 | 2015-10-16 13:51:51 -0500 | [diff] [blame] | 639 | |
| 640 | /* Erratum 619 - Family 15h Bx |
| 641 | * System software should set F5x88[14] to 1b. */ |
| 642 | { 5, 0x88, AMD_OR_B2, AMD_PTYPE_ALL, |
| 643 | 1 << 14, 1 << 14 }, |
Timothy Pearson | aab3ad2 | 2015-08-08 20:31:03 -0500 | [diff] [blame] | 644 | |
| 645 | /* L3 Control 2 */ |
| 646 | { 3, 0x1b8, AMD_FAM15_ALL, AMD_PTYPE_ALL, |
| 647 | 0x00000090, 0x000001d0 }, /* ImplRdProjDelayThresh = 0x2, |
| 648 | ImplRdAnySubUnavail = 0x1 */ |
Marc Jones | c74e362 | 2008-04-22 23:09:34 +0000 | [diff] [blame] | 649 | }; |
| 650 | |
| 651 | |
| 652 | /* |
| 653 | * Default HyperTransport Phy and errata settings. |
| 654 | */ |
| 655 | static const struct { |
| 656 | u16 htreg; /* HT Phy Register index */ |
Timothy Pearson | 730a043 | 2015-10-16 13:51:51 -0500 | [diff] [blame] | 657 | uint64_t revision; |
Marc Jones | c74e362 | 2008-04-22 23:09:34 +0000 | [diff] [blame] | 658 | u32 platform; |
| 659 | u32 linktype; |
| 660 | u32 data; |
| 661 | u32 mask; |
| 662 | } fam10_htphy_default[] = { |
| 663 | |
Zheng Bao | 2ca2f17 | 2011-03-28 04:29:14 +0000 | [diff] [blame] | 664 | /* Errata 344 - Fam10 C2/C3, D0/D1 |
Marc Jones | aac8dc8 | 2009-06-17 15:33:57 +0000 | [diff] [blame] | 665 | * System software should set bit 6 of F4x1[9C, 94, 8C, 84]_x[78:70, 68:60]. */ |
Zheng Bao | 2ca2f17 | 2011-03-28 04:29:14 +0000 | [diff] [blame] | 666 | { 0x60, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, |
Marc Jones | aac8dc8 | 2009-06-17 15:33:57 +0000 | [diff] [blame] | 667 | 0x00000040, 0x00000040 }, |
Zheng Bao | 2ca2f17 | 2011-03-28 04:29:14 +0000 | [diff] [blame] | 668 | { 0x61, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, |
Marc Jones | aac8dc8 | 2009-06-17 15:33:57 +0000 | [diff] [blame] | 669 | 0x00000040, 0x00000040 }, |
Zheng Bao | 2ca2f17 | 2011-03-28 04:29:14 +0000 | [diff] [blame] | 670 | { 0x62, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, |
Marc Jones | aac8dc8 | 2009-06-17 15:33:57 +0000 | [diff] [blame] | 671 | 0x00000040, 0x00000040 }, |
Zheng Bao | 2ca2f17 | 2011-03-28 04:29:14 +0000 | [diff] [blame] | 672 | { 0x63, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, |
Marc Jones | aac8dc8 | 2009-06-17 15:33:57 +0000 | [diff] [blame] | 673 | 0x00000040, 0x00000040 }, |
Zheng Bao | 2ca2f17 | 2011-03-28 04:29:14 +0000 | [diff] [blame] | 674 | { 0x64, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, |
Marc Jones | aac8dc8 | 2009-06-17 15:33:57 +0000 | [diff] [blame] | 675 | 0x00000040, 0x00000040 }, |
Zheng Bao | 2ca2f17 | 2011-03-28 04:29:14 +0000 | [diff] [blame] | 676 | { 0x65, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, |
Marc Jones | aac8dc8 | 2009-06-17 15:33:57 +0000 | [diff] [blame] | 677 | 0x00000040, 0x00000040 }, |
Zheng Bao | 2ca2f17 | 2011-03-28 04:29:14 +0000 | [diff] [blame] | 678 | { 0x66, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, |
Marc Jones | aac8dc8 | 2009-06-17 15:33:57 +0000 | [diff] [blame] | 679 | 0x00000040, 0x00000040 }, |
Zheng Bao | 2ca2f17 | 2011-03-28 04:29:14 +0000 | [diff] [blame] | 680 | { 0x67, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, |
Marc Jones | aac8dc8 | 2009-06-17 15:33:57 +0000 | [diff] [blame] | 681 | 0x00000040, 0x00000040 }, |
Zheng Bao | 2ca2f17 | 2011-03-28 04:29:14 +0000 | [diff] [blame] | 682 | { 0x68, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, |
Marc Jones | aac8dc8 | 2009-06-17 15:33:57 +0000 | [diff] [blame] | 683 | 0x00000040, 0x00000040 }, |
| 684 | |
Zheng Bao | 2ca2f17 | 2011-03-28 04:29:14 +0000 | [diff] [blame] | 685 | { 0x70, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, |
Marc Jones | aac8dc8 | 2009-06-17 15:33:57 +0000 | [diff] [blame] | 686 | 0x00000040, 0x00000040 }, |
Zheng Bao | 2ca2f17 | 2011-03-28 04:29:14 +0000 | [diff] [blame] | 687 | { 0x71, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, |
Marc Jones | aac8dc8 | 2009-06-17 15:33:57 +0000 | [diff] [blame] | 688 | 0x00000040, 0x00000040 }, |
Zheng Bao | 2ca2f17 | 2011-03-28 04:29:14 +0000 | [diff] [blame] | 689 | { 0x72, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, |
Marc Jones | aac8dc8 | 2009-06-17 15:33:57 +0000 | [diff] [blame] | 690 | 0x00000040, 0x00000040 }, |
Zheng Bao | 2ca2f17 | 2011-03-28 04:29:14 +0000 | [diff] [blame] | 691 | { 0x73, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, |
Marc Jones | aac8dc8 | 2009-06-17 15:33:57 +0000 | [diff] [blame] | 692 | 0x00000040, 0x00000040 }, |
Zheng Bao | 2ca2f17 | 2011-03-28 04:29:14 +0000 | [diff] [blame] | 693 | { 0x74, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, |
Marc Jones | aac8dc8 | 2009-06-17 15:33:57 +0000 | [diff] [blame] | 694 | 0x00000040, 0x00000040 }, |
Zheng Bao | 2ca2f17 | 2011-03-28 04:29:14 +0000 | [diff] [blame] | 695 | { 0x75, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, |
Marc Jones | aac8dc8 | 2009-06-17 15:33:57 +0000 | [diff] [blame] | 696 | 0x00000040, 0x00000040 }, |
Zheng Bao | 2ca2f17 | 2011-03-28 04:29:14 +0000 | [diff] [blame] | 697 | { 0x76, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, |
Marc Jones | aac8dc8 | 2009-06-17 15:33:57 +0000 | [diff] [blame] | 698 | 0x00000040, 0x00000040 }, |
Zheng Bao | 2ca2f17 | 2011-03-28 04:29:14 +0000 | [diff] [blame] | 699 | { 0x77, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, |
Marc Jones | aac8dc8 | 2009-06-17 15:33:57 +0000 | [diff] [blame] | 700 | 0x00000040, 0x00000040 }, |
Zheng Bao | 2ca2f17 | 2011-03-28 04:29:14 +0000 | [diff] [blame] | 701 | { 0x78, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, |
Marc Jones | aac8dc8 | 2009-06-17 15:33:57 +0000 | [diff] [blame] | 702 | 0x00000040, 0x00000040 }, |
| 703 | |
Zheng Bao | 2ca2f17 | 2011-03-28 04:29:14 +0000 | [diff] [blame] | 704 | /* Errata 354 - Fam10 C2, C3 |
Marc Jones | aac8dc8 | 2009-06-17 15:33:57 +0000 | [diff] [blame] | 705 | * System software should set bit 6 of F4x1[9C,94,8C,84]_x[58:50, 48:40] for all links. */ |
Zheng Bao | 2ca2f17 | 2011-03-28 04:29:14 +0000 | [diff] [blame] | 706 | { 0x40, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, |
Marc Jones | aac8dc8 | 2009-06-17 15:33:57 +0000 | [diff] [blame] | 707 | 0x00000040, 0x00000040 }, |
Zheng Bao | 2ca2f17 | 2011-03-28 04:29:14 +0000 | [diff] [blame] | 708 | { 0x41, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, |
Marc Jones | aac8dc8 | 2009-06-17 15:33:57 +0000 | [diff] [blame] | 709 | 0x00000040, 0x00000040 }, |
Zheng Bao | 2ca2f17 | 2011-03-28 04:29:14 +0000 | [diff] [blame] | 710 | { 0x42, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, |
Marc Jones | aac8dc8 | 2009-06-17 15:33:57 +0000 | [diff] [blame] | 711 | 0x00000040, 0x00000040 }, |
Zheng Bao | 2ca2f17 | 2011-03-28 04:29:14 +0000 | [diff] [blame] | 712 | { 0x43, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, |
Marc Jones | aac8dc8 | 2009-06-17 15:33:57 +0000 | [diff] [blame] | 713 | 0x00000040, 0x00000040 }, |
Zheng Bao | 2ca2f17 | 2011-03-28 04:29:14 +0000 | [diff] [blame] | 714 | { 0x44, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, |
Marc Jones | aac8dc8 | 2009-06-17 15:33:57 +0000 | [diff] [blame] | 715 | 0x00000040, 0x00000040 }, |
Zheng Bao | 2ca2f17 | 2011-03-28 04:29:14 +0000 | [diff] [blame] | 716 | { 0x45, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, |
Marc Jones | aac8dc8 | 2009-06-17 15:33:57 +0000 | [diff] [blame] | 717 | 0x00000040, 0x00000040 }, |
Zheng Bao | 2ca2f17 | 2011-03-28 04:29:14 +0000 | [diff] [blame] | 718 | { 0x46, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, |
Marc Jones | aac8dc8 | 2009-06-17 15:33:57 +0000 | [diff] [blame] | 719 | 0x00000040, 0x00000040 }, |
Zheng Bao | 2ca2f17 | 2011-03-28 04:29:14 +0000 | [diff] [blame] | 720 | { 0x47, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, |
Marc Jones | aac8dc8 | 2009-06-17 15:33:57 +0000 | [diff] [blame] | 721 | 0x00000040, 0x00000040 }, |
Zheng Bao | 2ca2f17 | 2011-03-28 04:29:14 +0000 | [diff] [blame] | 722 | { 0x48, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, |
Marc Jones | aac8dc8 | 2009-06-17 15:33:57 +0000 | [diff] [blame] | 723 | 0x00000040, 0x00000040 }, |
| 724 | |
Zheng Bao | 2ca2f17 | 2011-03-28 04:29:14 +0000 | [diff] [blame] | 725 | { 0x50, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, |
Marc Jones | aac8dc8 | 2009-06-17 15:33:57 +0000 | [diff] [blame] | 726 | 0x00000040, 0x00000040 }, |
Zheng Bao | 2ca2f17 | 2011-03-28 04:29:14 +0000 | [diff] [blame] | 727 | { 0x51, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, |
Marc Jones | aac8dc8 | 2009-06-17 15:33:57 +0000 | [diff] [blame] | 728 | 0x00000040, 0x00000040 }, |
Zheng Bao | 2ca2f17 | 2011-03-28 04:29:14 +0000 | [diff] [blame] | 729 | { 0x52, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, |
Marc Jones | aac8dc8 | 2009-06-17 15:33:57 +0000 | [diff] [blame] | 730 | 0x00000040, 0x00000040 }, |
Zheng Bao | 2ca2f17 | 2011-03-28 04:29:14 +0000 | [diff] [blame] | 731 | { 0x53, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, |
Marc Jones | aac8dc8 | 2009-06-17 15:33:57 +0000 | [diff] [blame] | 732 | 0x00000040, 0x00000040 }, |
Zheng Bao | 2ca2f17 | 2011-03-28 04:29:14 +0000 | [diff] [blame] | 733 | { 0x54, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, |
Marc Jones | aac8dc8 | 2009-06-17 15:33:57 +0000 | [diff] [blame] | 734 | 0x00000040, 0x00000040 }, |
Zheng Bao | 2ca2f17 | 2011-03-28 04:29:14 +0000 | [diff] [blame] | 735 | { 0x55, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, |
Marc Jones | aac8dc8 | 2009-06-17 15:33:57 +0000 | [diff] [blame] | 736 | 0x00000040, 0x00000040 }, |
Zheng Bao | 2ca2f17 | 2011-03-28 04:29:14 +0000 | [diff] [blame] | 737 | { 0x56, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, |
Marc Jones | aac8dc8 | 2009-06-17 15:33:57 +0000 | [diff] [blame] | 738 | 0x00000040, 0x00000040 }, |
Zheng Bao | 2ca2f17 | 2011-03-28 04:29:14 +0000 | [diff] [blame] | 739 | { 0x57, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, |
Marc Jones | aac8dc8 | 2009-06-17 15:33:57 +0000 | [diff] [blame] | 740 | 0x00000040, 0x00000040 }, |
Zheng Bao | 2ca2f17 | 2011-03-28 04:29:14 +0000 | [diff] [blame] | 741 | { 0x58, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, |
Marc Jones | aac8dc8 | 2009-06-17 15:33:57 +0000 | [diff] [blame] | 742 | 0x00000040, 0x00000040 }, |
| 743 | |
Zheng Bao | 2ca2f17 | 2011-03-28 04:29:14 +0000 | [diff] [blame] | 744 | /* Errata 327 - Fam10 C2/C3, D0/D1 |
Marc Jones | aac8dc8 | 2009-06-17 15:33:57 +0000 | [diff] [blame] | 745 | * BIOS should set the Link Phy Impedance Register[RttCtl] |
| 746 | * (F4x1[9C, 94, 8C, 84]_x[D0, C0][31:29]) to 010b and |
| 747 | * Link Phy Impedance Register[RttIndex] |
| 748 | * (F4x1[9C, 94, 8C, 84]_x[D0, C0][20:16]) to 00100b */ |
Zheng Bao | 2ca2f17 | 2011-03-28 04:29:14 +0000 | [diff] [blame] | 749 | { 0xC0, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, |
Marc Jones | aac8dc8 | 2009-06-17 15:33:57 +0000 | [diff] [blame] | 750 | 0x40040000, 0xe01F0000 }, |
Zheng Bao | 2ca2f17 | 2011-03-28 04:29:14 +0000 | [diff] [blame] | 751 | { 0xD0, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, |
Marc Jones | aac8dc8 | 2009-06-17 15:33:57 +0000 | [diff] [blame] | 752 | 0x40040000, 0xe01F0000 }, |
| 753 | |
Zheng Bao | 2ca2f17 | 2011-03-28 04:29:14 +0000 | [diff] [blame] | 754 | { 0x520A,AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, |
Marc Jones | aac8dc8 | 2009-06-17 15:33:57 +0000 | [diff] [blame] | 755 | 0x00004000, 0x00006000 }, /* HT_PHY_DLL_REG */ |
| 756 | |
Zheng Bao | 2ca2f17 | 2011-03-28 04:29:14 +0000 | [diff] [blame] | 757 | { 0x530A, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, |
Marc Jones | aac8dc8 | 2009-06-17 15:33:57 +0000 | [diff] [blame] | 758 | 0x00004000, 0x00006000 }, /* HT_PHY_DLL_REG */ |
| 759 | |
| 760 | { 0x520A, AMD_DR_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, |
Marc Jones | c74e362 | 2008-04-22 23:09:34 +0000 | [diff] [blame] | 761 | 0x00004400, 0x00006400 }, /* HT_PHY_DLL_REG */ |
| 762 | |
Marc Jones | aac8dc8 | 2009-06-17 15:33:57 +0000 | [diff] [blame] | 763 | { 0x530A, AMD_DR_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, |
Marc Jones | c74e362 | 2008-04-22 23:09:34 +0000 | [diff] [blame] | 764 | 0x00004400, 0x00006400 }, /* HT_PHY_DLL_REG */ |
| 765 | |
Timothy Pearson | 0122afb | 2015-07-30 14:07:15 -0500 | [diff] [blame] | 766 | { 0xCF, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3, |
Timothy Pearson | 51cfbcd | 2015-08-02 21:18:29 -0500 | [diff] [blame] | 767 | 0x0000005a, 0x000000ff }, /* Use common "safe" setting for K10 */ |
Marc Jones | c74e362 | 2008-04-22 23:09:34 +0000 | [diff] [blame] | 768 | |
Timothy Pearson | 0122afb | 2015-07-30 14:07:15 -0500 | [diff] [blame] | 769 | { 0xDF, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3, |
Timothy Pearson | 51cfbcd | 2015-08-02 21:18:29 -0500 | [diff] [blame] | 770 | 0x0000005a, 0x000000ff }, /* Use common "safe" setting for K10 */ |
Marc Jones | c74e362 | 2008-04-22 23:09:34 +0000 | [diff] [blame] | 771 | |
Timothy Pearson | 0122afb | 2015-07-30 14:07:15 -0500 | [diff] [blame] | 772 | { 0xCF, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1, |
Timothy Pearson | 51cfbcd | 2015-08-02 21:18:29 -0500 | [diff] [blame] | 773 | 0x0000006d, 0x000000ff }, /* HT_PHY_HT1_FIFO_PTR_OPT_VALUE */ |
Marc Jones | c74e362 | 2008-04-22 23:09:34 +0000 | [diff] [blame] | 774 | |
Timothy Pearson | 0122afb | 2015-07-30 14:07:15 -0500 | [diff] [blame] | 775 | { 0xDF, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1, |
Timothy Pearson | 51cfbcd | 2015-08-02 21:18:29 -0500 | [diff] [blame] | 776 | 0x0000006d, 0x000000ff }, /* HT_PHY_HT1_FIFO_PTR_OPT_VALUE */ |
Marc Jones | c74e362 | 2008-04-22 23:09:34 +0000 | [diff] [blame] | 777 | |
| 778 | /* Link Phy Receiver Loop Filter Registers */ |
Timothy Pearson | 0122afb | 2015-07-30 14:07:15 -0500 | [diff] [blame] | 779 | { 0xD1, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3, |
Marc Jones | c74e362 | 2008-04-22 23:09:34 +0000 | [diff] [blame] | 780 | 0x08040000, 0x3FFFC000 }, /* [29:22] LfcMax = 20h, |
| 781 | [21:14] LfcMin = 10h */ |
| 782 | |
Timothy Pearson | 0122afb | 2015-07-30 14:07:15 -0500 | [diff] [blame] | 783 | { 0xC1, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3, |
Marc Jones | c74e362 | 2008-04-22 23:09:34 +0000 | [diff] [blame] | 784 | 0x08040000, 0x3FFFC000 }, /* [29:22] LfcMax = 20h, |
| 785 | [21:14] LfcMin = 10h */ |
| 786 | |
Timothy Pearson | 0122afb | 2015-07-30 14:07:15 -0500 | [diff] [blame] | 787 | { 0xD1, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1, |
Marc Jones | c74e362 | 2008-04-22 23:09:34 +0000 | [diff] [blame] | 788 | 0x04020000, 0x3FFFC000 }, /* [29:22] LfcMax = 10h, |
| 789 | [21:14] LfcMin = 08h */ |
| 790 | |
Timothy Pearson | 0122afb | 2015-07-30 14:07:15 -0500 | [diff] [blame] | 791 | { 0xC1, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1, |
Marc Jones | c74e362 | 2008-04-22 23:09:34 +0000 | [diff] [blame] | 792 | 0x04020000, 0x3FFFC000 }, /* [29:22] LfcMax = 10h, |
| 793 | [21:14] LfcMin = 08h */ |
Marc Jones | aac8dc8 | 2009-06-17 15:33:57 +0000 | [diff] [blame] | 794 | |
Timothy Pearson | 0122afb | 2015-07-30 14:07:15 -0500 | [diff] [blame] | 795 | { 0xC0, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, |
Marc Jones | aac8dc8 | 2009-06-17 15:33:57 +0000 | [diff] [blame] | 796 | 0x40040000, 0xe01F0000 }, /* [31:29] RttCtl = 02h, |
Timothy Pearson | 0122afb | 2015-07-30 14:07:15 -0500 | [diff] [blame] | 797 | [20:16] RttIndex = 04h */ |
| 798 | |
Timothy Pearson | 0122afb | 2015-07-30 14:07:15 -0500 | [diff] [blame] | 799 | { 0xCF, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3, |
Timothy Pearson | 51cfbcd | 2015-08-02 21:18:29 -0500 | [diff] [blame] | 800 | 0x00000a2a, 0x000000ff }, /* P0RcvRdPtr = 0xa, |
| 801 | P0XmtRdPtr = 0x2 |
| 802 | P1RcvRdPtr = 0xa |
| 803 | P1XmtRdPtr = 0x0 */ |
Timothy Pearson | 0122afb | 2015-07-30 14:07:15 -0500 | [diff] [blame] | 804 | |
| 805 | { 0xDF, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3, |
Timothy Pearson | 51cfbcd | 2015-08-02 21:18:29 -0500 | [diff] [blame] | 806 | 0x00000a2a, 0x000000ff }, /* P0RcvRdPtr = 0xa, |
| 807 | P0XmtRdPtr = 0x2 |
| 808 | P1RcvRdPtr = 0xa |
| 809 | P1XmtRdPtr = 0x0 */ |
Timothy Pearson | 0122afb | 2015-07-30 14:07:15 -0500 | [diff] [blame] | 810 | |
| 811 | { 0xCF, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1, |
Timothy Pearson | 51cfbcd | 2015-08-02 21:18:29 -0500 | [diff] [blame] | 812 | 0x00000d4d, 0x000000ff }, /* P0RcvRdPtr = 0xd, |
| 813 | P0XmtRdPtr = 0x4 |
| 814 | P1RcvRdPtr = 0xd |
| 815 | P1XmtRdPtr = 0x0 */ |
Timothy Pearson | 0122afb | 2015-07-30 14:07:15 -0500 | [diff] [blame] | 816 | |
| 817 | { 0xDF, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1, |
Timothy Pearson | 51cfbcd | 2015-08-02 21:18:29 -0500 | [diff] [blame] | 818 | 0x00000d4d, 0x000000ff }, /* P0RcvRdPtr = 0xd, |
| 819 | P0XmtRdPtr = 0x4 |
| 820 | P1RcvRdPtr = 0xd |
| 821 | P1XmtRdPtr = 0x0 */ |
Timothy Pearson | 0122afb | 2015-07-30 14:07:15 -0500 | [diff] [blame] | 822 | |
| 823 | /* Link Phy Receiver Loop Filter Registers */ |
| 824 | { 0xD1, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3, |
| 825 | 0x08040000, 0x3FFFC000 }, /* [29:22] LfcMax = 20h, |
| 826 | [21:14] LfcMin = 10h */ |
| 827 | |
| 828 | { 0xC1, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3, |
| 829 | 0x08040000, 0x3FFFC000 }, /* [29:22] LfcMax = 20h, |
| 830 | [21:14] LfcMin = 10h */ |
| 831 | |
| 832 | { 0xD1, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1, |
| 833 | 0x04020000, 0x3FFFC000 }, /* [29:22] LfcMax = 10h, |
| 834 | [21:14] LfcMin = 08h */ |
| 835 | |
| 836 | { 0xC1, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1, |
| 837 | 0x04020000, 0x3FFFC000 }, /* [29:22] LfcMax = 10h, |
| 838 | [21:14] LfcMin = 08h */ |
| 839 | |
| 840 | { 0xC0, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, |
| 841 | 0x40040000, 0xe01F0000 }, /* [31:29] RttCtl = 02h, |
Timothy Pearson | 51cfbcd | 2015-08-02 21:18:29 -0500 | [diff] [blame] | 842 | [20:16] RttIndex = 04h */ |
Timothy Pearson | 2733846 | 2015-09-13 15:54:32 -0500 | [diff] [blame] | 843 | |
| 844 | { 0xc4, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3, |
| 845 | 0x00013480, 0x0003fc80 }, /* [17:10] DCV = 0x4d, |
| 846 | [7] DfeEn = 0x1 */ |
| 847 | |
| 848 | { 0xd4, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3, |
| 849 | 0x00013480, 0x0003fc80 }, /* [17:10] DCV = 0x4d, |
| 850 | [7] DfeEn = 0x1 */ |
Marc Jones | c74e362 | 2008-04-22 23:09:34 +0000 | [diff] [blame] | 851 | }; |