Alexandru Gagniuc | f64111b | 2013-12-13 20:44:48 -0600 | [diff] [blame] | 1 | /* |
| 2 | * Uart setup helpers for Allwinner SoCs |
| 3 | * |
| 4 | * Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me@gmail.com> |
| 5 | * Subject to the GNU GPL v2, or (at your option) any later version. |
| 6 | */ |
| 7 | |
| 8 | #include "uart.h" |
| 9 | #include <arch/io.h> |
Kyösti Mälkki | 1d7541f | 2014-02-17 21:34:42 +0200 | [diff] [blame] | 10 | #include <console/uart.h> |
Kyösti Mälkki | bea6bf0 | 2014-01-30 15:45:16 +0200 | [diff] [blame] | 11 | #include <drivers/uart/uart8250reg.h> |
Alexandru Gagniuc | f64111b | 2013-12-13 20:44:48 -0600 | [diff] [blame] | 12 | |
| 13 | /** |
| 14 | * \brief Configure line control settings for UART |
| 15 | */ |
Kyösti Mälkki | 28837c6 | 2014-04-04 20:32:59 +0300 | [diff] [blame] | 16 | static void a10_uart_configure(struct a10_uart *uart, u32 baud_rate, u8 data_bits, |
Alexandru Gagniuc | f64111b | 2013-12-13 20:44:48 -0600 | [diff] [blame] | 17 | enum uart_parity parity, u8 stop_bits) |
| 18 | { |
| 19 | u32 reg32; |
| 20 | u16 div; |
Alexandru Gagniuc | f64111b | 2013-12-13 20:44:48 -0600 | [diff] [blame] | 21 | |
Kyösti Mälkki | 65ba20e | 2014-02-19 08:58:12 +0200 | [diff] [blame] | 22 | div = (u16) uart_baudrate_divisor(baud_rate, |
| 23 | uart_platform_refclk(), 16); |
Alexandru Gagniuc | f64111b | 2013-12-13 20:44:48 -0600 | [diff] [blame] | 24 | /* Enable access to Divisor Latch register */ |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 25 | write32(&uart->lcr, UART8250_LCR_DLAB); |
Alexandru Gagniuc | f64111b | 2013-12-13 20:44:48 -0600 | [diff] [blame] | 26 | /* Set baudrate */ |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 27 | write32(&uart->dlh, (div >> 8) & 0xff); |
| 28 | write32(&uart->dll, div & 0xff); |
Alexandru Gagniuc | f64111b | 2013-12-13 20:44:48 -0600 | [diff] [blame] | 29 | /* Set line control */ |
Gabe Black | 77ffa0d | 2013-09-30 21:25:49 -0700 | [diff] [blame] | 30 | reg32 = (data_bits - 5) & UART8250_LCR_WLS_MSK; |
Alexandru Gagniuc | f64111b | 2013-12-13 20:44:48 -0600 | [diff] [blame] | 31 | switch (parity) { |
| 32 | case UART_PARITY_ODD: |
Gabe Black | 77ffa0d | 2013-09-30 21:25:49 -0700 | [diff] [blame] | 33 | reg32 |= UART8250_LCR_PEN; |
Alexandru Gagniuc | f64111b | 2013-12-13 20:44:48 -0600 | [diff] [blame] | 34 | break; |
| 35 | case UART_PARITY_EVEN: |
Gabe Black | 77ffa0d | 2013-09-30 21:25:49 -0700 | [diff] [blame] | 36 | reg32 |= UART8250_LCR_PEN; |
| 37 | reg32 |= UART8250_LCR_EPS; |
Alexandru Gagniuc | f64111b | 2013-12-13 20:44:48 -0600 | [diff] [blame] | 38 | break; |
| 39 | case UART_PARITY_NONE: /* Fall through */ |
| 40 | default: |
| 41 | break; |
| 42 | } |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 43 | write32(&uart->lcr, reg32); |
Alexandru Gagniuc | f64111b | 2013-12-13 20:44:48 -0600 | [diff] [blame] | 44 | } |
| 45 | |
Kyösti Mälkki | 28837c6 | 2014-04-04 20:32:59 +0300 | [diff] [blame] | 46 | static void a10_uart_enable_fifos(struct a10_uart *uart) |
Alexandru Gagniuc | f64111b | 2013-12-13 20:44:48 -0600 | [diff] [blame] | 47 | { |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 48 | write32(&uart->fcr, UART8250_FCR_FIFO_EN); |
Alexandru Gagniuc | f64111b | 2013-12-13 20:44:48 -0600 | [diff] [blame] | 49 | } |
| 50 | |
| 51 | static int tx_fifo_full(struct a10_uart *uart) |
| 52 | { |
| 53 | /* This may be a misnomer, or a typo in the datasheet. THRE indicates |
| 54 | * that the TX register is empty, not that the FIFO is not full, but |
| 55 | * this may be due to a datasheet typo. Keep the current name to signal |
| 56 | * intent. */ |
Gabe Black | 77ffa0d | 2013-09-30 21:25:49 -0700 | [diff] [blame] | 57 | return !(read32(&uart->lsr) & UART8250_LSR_THRE); |
Alexandru Gagniuc | f64111b | 2013-12-13 20:44:48 -0600 | [diff] [blame] | 58 | } |
| 59 | |
| 60 | static int rx_fifo_empty(struct a10_uart *uart) |
| 61 | { |
Gabe Black | 77ffa0d | 2013-09-30 21:25:49 -0700 | [diff] [blame] | 62 | return !(read32(&uart->lsr) & UART8250_LSR_DR); |
Alexandru Gagniuc | f64111b | 2013-12-13 20:44:48 -0600 | [diff] [blame] | 63 | } |
| 64 | |
| 65 | /** |
| 66 | * \brief Read a single byte from the UART. |
| 67 | * |
| 68 | * Blocks until at least a byte is available. |
| 69 | */ |
Kyösti Mälkki | 28837c6 | 2014-04-04 20:32:59 +0300 | [diff] [blame] | 70 | static u8 a10_uart_rx_blocking(struct a10_uart *uart) |
Alexandru Gagniuc | f64111b | 2013-12-13 20:44:48 -0600 | [diff] [blame] | 71 | { |
Alexandru Gagniuc | f64111b | 2013-12-13 20:44:48 -0600 | [diff] [blame] | 72 | while (rx_fifo_empty(uart)) ; |
| 73 | |
| 74 | return read32(&uart->rbr); |
| 75 | } |
| 76 | |
| 77 | /** |
| 78 | * \brief Write a single byte to the UART. |
| 79 | * |
| 80 | * Blocks until there is space in the FIFO. |
| 81 | */ |
Kyösti Mälkki | 28837c6 | 2014-04-04 20:32:59 +0300 | [diff] [blame] | 82 | static void a10_uart_tx_blocking(struct a10_uart *uart, u8 data) |
Alexandru Gagniuc | f64111b | 2013-12-13 20:44:48 -0600 | [diff] [blame] | 83 | { |
Alexandru Gagniuc | f64111b | 2013-12-13 20:44:48 -0600 | [diff] [blame] | 84 | while (tx_fifo_full(uart)) ; |
| 85 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 86 | return write32(&uart->thr, data); |
Alexandru Gagniuc | f64111b | 2013-12-13 20:44:48 -0600 | [diff] [blame] | 87 | } |
Kyösti Mälkki | 28837c6 | 2014-04-04 20:32:59 +0300 | [diff] [blame] | 88 | |
| 89 | |
| 90 | void uart_init(int idx) |
| 91 | { |
| 92 | struct a10_uart *uart_base = uart_platform_baseptr(idx); |
| 93 | |
| 94 | /* Use default 8N1 encoding */ |
| 95 | a10_uart_configure(uart_base, default_baudrate(), |
| 96 | 8, UART_PARITY_NONE, 1); |
| 97 | a10_uart_enable_fifos(uart_base); |
| 98 | } |
| 99 | |
| 100 | unsigned char uart_rx_byte(int idx) |
| 101 | { |
| 102 | return a10_uart_rx_blocking(uart_platform_baseptr(idx)); |
| 103 | } |
| 104 | |
| 105 | void uart_tx_byte(int idx, unsigned char data) |
| 106 | { |
| 107 | a10_uart_tx_blocking(uart_platform_baseptr(idx), data); |
| 108 | } |
| 109 | |
| 110 | void uart_tx_flush(int idx) |
| 111 | { |
| 112 | } |