Alexandru Gagniuc | f64111b | 2013-12-13 20:44:48 -0600 | [diff] [blame] | 1 | /* |
Alexandru Gagniuc | bd09dbe | 2013-12-31 00:17:19 -0500 | [diff] [blame] | 2 | * Timer control and delays for Allwinner CPUs |
Alexandru Gagniuc | f64111b | 2013-12-13 20:44:48 -0600 | [diff] [blame] | 3 | * |
| 4 | * Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me@gmail.com> |
| 5 | * Subject to the GNU GPL v2, or (at your option) any later version. |
| 6 | */ |
| 7 | |
Alexandru Gagniuc | bd09dbe | 2013-12-31 00:17:19 -0500 | [diff] [blame] | 8 | #include "timer.h" |
| 9 | |
| 10 | #include <arch/io.h> |
Alexandru Gagniuc | f64111b | 2013-12-13 20:44:48 -0600 | [diff] [blame] | 11 | #include <delay.h> |
| 12 | #include <timer.h> |
| 13 | |
Alexandru Gagniuc | a94bed0 | 2014-01-02 01:57:53 -0500 | [diff] [blame] | 14 | struct a1x_timer_module *const timer_module = (void *)A1X_TIMER_BASE; |
Alexandru Gagniuc | bd09dbe | 2013-12-31 00:17:19 -0500 | [diff] [blame] | 15 | struct a1x_timer *const tmr0 = |
| 16 | &((struct a1x_timer_module *)A1X_TIMER_BASE)->timer[0]; |
| 17 | |
| 18 | static inline u32 read_timer(void) |
| 19 | { |
| 20 | return read32(&tmr0->val); |
| 21 | } |
| 22 | |
Alexandru Gagniuc | f64111b | 2013-12-13 20:44:48 -0600 | [diff] [blame] | 23 | void init_timer(void) |
| 24 | { |
Alexandru Gagniuc | bd09dbe | 2013-12-31 00:17:19 -0500 | [diff] [blame] | 25 | u32 reg32; |
| 26 | /* Load the timer rollover value */ |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 27 | write32(&tmr0->interval, 0xffffffff); |
Alexandru Gagniuc | bd09dbe | 2013-12-31 00:17:19 -0500 | [diff] [blame] | 28 | /* Configure the timer to run from 24MHz oscillator, no prescaler */ |
| 29 | reg32 = TIMER_CTRL_PRESC_DIV_EXP(0); |
| 30 | reg32 |= TIMER_CTRL_CLK_SRC_OSC24M; |
| 31 | reg32 |= TIMER_CTRL_RELOAD; |
| 32 | reg32 |= TIMER_CTRL_TMR_EN; |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 33 | write32(&tmr0->ctrl, reg32); |
Alexandru Gagniuc | f64111b | 2013-12-13 20:44:48 -0600 | [diff] [blame] | 34 | } |
| 35 | |
| 36 | void udelay(unsigned usec) |
| 37 | { |
Alexandru Gagniuc | bd09dbe | 2013-12-31 00:17:19 -0500 | [diff] [blame] | 38 | u32 curr_tick, last_tick; |
| 39 | s32 ticks_left; |
| 40 | |
| 41 | last_tick = read_timer(); |
| 42 | /* 24 timer ticks per microsecond (24 MHz, divided by 1) */ |
| 43 | ticks_left = usec * 24; |
| 44 | |
| 45 | /* FIXME: Should we consider timer rollover? |
| 46 | * From when we start the timer, we have almost three minutes before it |
| 47 | * rolls over, so we should be long into having booted our payload. |
| 48 | */ |
| 49 | while (ticks_left > 0) { |
| 50 | curr_tick = read_timer(); |
| 51 | /* Timer value decreases with each tick */ |
| 52 | ticks_left -= last_tick - curr_tick; |
| 53 | last_tick = curr_tick; |
| 54 | } |
| 55 | |
Alexandru Gagniuc | f64111b | 2013-12-13 20:44:48 -0600 | [diff] [blame] | 56 | } |
Alexandru Gagniuc | a94bed0 | 2014-01-02 01:57:53 -0500 | [diff] [blame] | 57 | |
| 58 | /* |
| 59 | * This function has nothing to do with timers; however, the chip revision |
| 60 | * register is in the timer module, so keep this function here. |
| 61 | */ |
| 62 | u8 a1x_get_cpu_chip_revision(void) |
| 63 | { |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 64 | write32(&timer_module->cpu_cfg, 0); |
Alexandru Gagniuc | a94bed0 | 2014-01-02 01:57:53 -0500 | [diff] [blame] | 65 | return (read32(&timer_module->cpu_cfg) >> 6) & 0x3; |
| 66 | } |