Daisuke Nojiri | af3b2a1 | 2014-10-23 12:39:11 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright 2014 Google Inc. |
| 5 | * |
| 6 | * Redistribution and use in source and binary forms, with or without |
| 7 | * modification, are permitted provided that the following conditions |
| 8 | * are met: |
| 9 | * 1. Redistributions of source code must retain the above copyright |
| 10 | * notice, this list of conditions and the following disclaimer. |
| 11 | * 2. Redistributions in binary form must reproduce the above copyright |
| 12 | * notice, this list of conditions and the following disclaimer in the |
| 13 | * documentation and/or other materials provided with the distribution. |
| 14 | * 3. The name of the author may not be used to endorse or promote products |
| 15 | * derived from this software without specific prior written permission. |
| 16 | * |
| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
| 18 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 19 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 20 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
| 21 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| 22 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
| 23 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
| 24 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
| 25 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
| 26 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
| 27 | * SUCH DAMAGE. |
| 28 | * |
| 29 | * cache.c: Cache maintenance routines for ARMv7-M |
| 30 | */ |
| 31 | |
| 32 | #include <stdint.h> |
| 33 | |
| 34 | #include <arch/cache.h> |
| 35 | |
| 36 | void tlb_invalidate_all(void) |
| 37 | { |
| 38 | } |
| 39 | |
| 40 | void dcache_clean_all(void) |
| 41 | { |
| 42 | } |
| 43 | |
| 44 | void dcache_clean_invalidate_all(void) |
| 45 | { |
| 46 | } |
| 47 | |
| 48 | void dcache_invalidate_all(void) |
| 49 | { |
| 50 | } |
| 51 | |
| 52 | unsigned int dcache_line_bytes(void) |
| 53 | { |
| 54 | return 0; |
| 55 | } |
| 56 | |
| 57 | void dcache_clean_by_mva(void const *addr, size_t len) |
| 58 | { |
| 59 | } |
| 60 | |
| 61 | void dcache_clean_invalidate_by_mva(void const *addr, size_t len) |
| 62 | { |
| 63 | } |
| 64 | |
| 65 | void dcache_invalidate_by_mva(void const *addr, size_t len) |
| 66 | { |
| 67 | } |
| 68 | |
| 69 | void dcache_mmu_disable(void) |
| 70 | { |
| 71 | } |
| 72 | |
| 73 | void dcache_mmu_enable(void) |
| 74 | { |
| 75 | } |
| 76 | |
| 77 | void cache_sync_instructions(void) |
| 78 | { |
| 79 | } |