huang lin | 41e2499 | 2015-05-20 17:27:10 +0800 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2015 Rockchip Electronics |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
huang lin | 41e2499 | 2015-05-20 17:27:10 +0800 | [diff] [blame] | 14 | */ |
| 15 | |
| 16 | #include <libpayload.h> |
| 17 | #include <assert.h> |
| 18 | #include <limits.h> |
| 19 | |
| 20 | #include <udc/dwc2_udc.h> |
| 21 | #include "dwc2_priv.h" |
| 22 | |
| 23 | static int get_mps(dwc2_ep_t *ep) |
| 24 | { |
| 25 | dwc2_ep_reg_t *ep_reg = ep->ep_regs; |
| 26 | depctl_t depctl; |
| 27 | uint16_t mps = 0; |
| 28 | |
| 29 | depctl.d32 = readl(&ep_reg->depctl); |
| 30 | if (ep->ep_num == 0) { |
| 31 | switch (depctl.mps) { |
| 32 | case D0EPCTL_MPS_64: |
| 33 | mps = 64; |
| 34 | break; |
| 35 | case D0EPCTL_MPS_32: |
| 36 | mps = 32; |
| 37 | break; |
| 38 | case D0EPCTL_MPS_16: |
| 39 | mps = 16; |
| 40 | break; |
| 41 | case D0EPCTL_MPS_8: |
| 42 | mps = 8; |
| 43 | break; |
| 44 | default: |
| 45 | usb_debug("get mps error\n"); |
| 46 | } |
| 47 | } else { |
| 48 | mps = depctl.mps; |
| 49 | } |
| 50 | |
| 51 | return mps; |
| 52 | } |
| 53 | |
| 54 | static void dwc2_process_ep(dwc2_ep_t *ep, int len, void *buf) |
| 55 | { |
| 56 | depctl_t depctl; |
| 57 | depsiz_t depsiz; |
| 58 | uint16_t pkt_cnt; |
| 59 | uint16_t mps; |
| 60 | int max_transfer_size; |
| 61 | dwc2_ep_reg_t *ep_reg = ep->ep_regs; |
| 62 | |
| 63 | if (ep->ep_num == 0) |
| 64 | max_transfer_size = EP0_MAXLEN; |
| 65 | else |
| 66 | max_transfer_size = EP_MAXLEN; |
| 67 | assert(len <= max_transfer_size); |
| 68 | |
| 69 | mps = get_mps(ep); |
| 70 | |
| 71 | pkt_cnt = ALIGN_UP(len, mps) / mps; |
| 72 | if (pkt_cnt == 0) |
| 73 | pkt_cnt = 1; |
| 74 | |
| 75 | depsiz.pktcnt = pkt_cnt; |
| 76 | depsiz.xfersize = len; |
| 77 | writel(depsiz.d32, &ep_reg->deptsiz); |
| 78 | |
| 79 | writel((uint32_t)buf, &ep_reg->depdma); |
| 80 | |
| 81 | depctl.d32 = readl(&ep_reg->depctl); |
| 82 | |
| 83 | if (ep->ep_num != 0) { |
| 84 | if (depctl.dpid == 0) |
| 85 | depctl.setd0pid = 1; |
| 86 | else |
| 87 | depctl.setd1pid = 1; |
| 88 | } |
| 89 | depctl.cnak = 1; |
| 90 | depctl.epena = 1; |
| 91 | writel(depctl.d32, &ep_reg->depctl); |
| 92 | |
| 93 | } |
| 94 | |
| 95 | static void dwc2_write_ep(dwc2_ep_t *ep, int len, void *buf) |
| 96 | { |
| 97 | dwc2_process_ep(ep, len, buf); |
| 98 | } |
| 99 | |
| 100 | static void dwc2_read_ep(dwc2_ep_t *ep, int len, void *buf) |
| 101 | { |
| 102 | dwc2_process_ep(ep, len, buf); |
| 103 | } |
| 104 | |
| 105 | static void dwc2_connect(struct usbdev_ctrl *this, int connect) |
| 106 | { |
| 107 | /* Turn on the USB connection by enabling the pullup resistor */ |
| 108 | dwc2_pdata_t *p = DWC2_PDATA(this); |
| 109 | dctl_t dctl; |
| 110 | |
| 111 | usb_debug("DwcUdcConnect\n"); |
| 112 | |
| 113 | dctl.d32 = readl(&p->regs->device.dctl); |
| 114 | |
| 115 | if (connect) |
| 116 | /* Connect */ |
| 117 | dctl.sftdiscon = 0; |
| 118 | else |
| 119 | /* Disconnect */ |
| 120 | dctl.sftdiscon = 1; |
| 121 | |
| 122 | writel(dctl.d32, &p->regs->device.dctl); |
| 123 | } |
| 124 | |
| 125 | static void dwc2_bus_reset(struct usbdev_ctrl *this) |
| 126 | { |
| 127 | dwc2_pdata_t *p = DWC2_PDATA(this); |
| 128 | dcfg_t dcfg; |
| 129 | dctl_t dctl; |
| 130 | |
| 131 | if (this->initialized) |
| 132 | this->initialized = 0; |
| 133 | |
| 134 | /* Reset device addr */ |
| 135 | dcfg.d32 = readl(&p->regs->device.dcfg); |
| 136 | dcfg.devaddr = 0; |
| 137 | writel(dcfg.d32, &p->regs->device.dcfg); |
| 138 | |
| 139 | dctl.d32 = readl(&p->regs->device.dctl); |
| 140 | dctl.rmtwkupsig = 0; |
| 141 | writel(dctl.d32, &p->regs->device.dctl); |
| 142 | } |
| 143 | |
| 144 | static void dwc2_enum_done(struct usbdev_ctrl *this) |
| 145 | { |
| 146 | dwc2_pdata_t *p = DWC2_PDATA(this); |
| 147 | |
| 148 | dctl_t dctl; |
| 149 | dsts_t dsts; |
| 150 | |
| 151 | usb_debug("dwc2_enum_done\n"); |
| 152 | |
| 153 | dsts.d32 = readl(&p->regs->device.dsts); |
| 154 | |
| 155 | switch (dsts.enumspd) { |
| 156 | case 0: |
| 157 | this->ep_mps[0][0] = 64; |
| 158 | this->ep_mps[0][1] = 64; |
| 159 | usb_debug("HighSpeed Enum Done\n"); |
| 160 | break; |
| 161 | default: |
| 162 | usb_debug("EnumSpeed Error\n"); |
| 163 | return; |
| 164 | } |
| 165 | |
| 166 | /* Clear global IN Nak */ |
| 167 | dctl.d32 = readl(&p->regs->device.dctl); |
| 168 | dctl.cgnpinnak = 1; |
| 169 | writel(dctl.d32, &p->regs->device.dctl); |
| 170 | } |
| 171 | |
| 172 | static void dwc2_tx_fifo_flush(struct usbdev_ctrl *this, unsigned int idx) |
| 173 | { |
| 174 | dwc2_pdata_t *p = DWC2_PDATA(this); |
| 175 | grstctl_t grstctl; |
| 176 | int timeout = 100; |
| 177 | |
| 178 | grstctl.d32 = readl(&p->regs->core.grstctl); |
| 179 | grstctl.txfflsh = 1; |
| 180 | grstctl.txfnum = idx; |
| 181 | writel(grstctl.d32, &p->regs->core.grstctl); |
| 182 | |
| 183 | /* wait until the fifo is flushed */ |
| 184 | do { |
| 185 | udelay(1); |
| 186 | grstctl.d32 = readl(&p->regs->core.grstctl); |
| 187 | |
| 188 | if (--timeout < 0) { |
| 189 | usb_debug("timeout flushing Tx fifo %x\n", idx); |
| 190 | break; |
| 191 | } |
| 192 | } while (grstctl.txfflsh); |
| 193 | } |
| 194 | |
| 195 | static void dwc2_rx_fifo_flush(struct usbdev_ctrl *this, unsigned int idx) |
| 196 | { |
| 197 | dwc2_pdata_t *p = DWC2_PDATA(this); |
| 198 | grstctl_t grstctl; |
| 199 | int timeout = 100; |
| 200 | |
| 201 | grstctl.d32 = readl(&p->regs->core.grstctl); |
| 202 | grstctl.rxfflsh = 1; |
| 203 | writel(grstctl.d32, &p->regs->core.grstctl); |
| 204 | |
| 205 | /* wait until the fifo is flushed */ |
| 206 | do { |
| 207 | udelay(1); |
| 208 | grstctl.d32 = readl(&p->regs->core.grstctl); |
| 209 | |
| 210 | if (--timeout < 0) { |
| 211 | usb_debug("timeout flushing Rx fifo %x\n", idx); |
| 212 | break; |
| 213 | } |
| 214 | } while (grstctl.rxfflsh); |
| 215 | } |
| 216 | |
| 217 | static void dwc2_disable_ep(dwc2_ep_reg_t *ep_reg) |
| 218 | { |
| 219 | depctl_t depctl; |
| 220 | depint_t depint; |
| 221 | |
| 222 | /* Disable the required IN/OUT endpoint */ |
| 223 | depctl.d32 = readl(&ep_reg->depctl); |
| 224 | |
| 225 | /* Already disabled */ |
| 226 | if (depctl.epena == 0) |
| 227 | return; |
| 228 | depctl.epdis = 1; |
| 229 | depctl.snak = 1; |
| 230 | writel(depctl.d32, &ep_reg->depctl); |
| 231 | |
| 232 | /* Wait for the DEPINTn.EPDisabled interrupt */ |
| 233 | do { |
| 234 | depint.d32 = readl(&ep_reg->depint); |
| 235 | } while (!depint.epdisbld); |
| 236 | |
| 237 | /* Clear DEPINTn.EPDisabled */ |
| 238 | writel(depint.d32, &ep_reg->depint); |
| 239 | |
| 240 | depctl.d32 = readl(&ep_reg->depctl); |
| 241 | depctl.epena = 0; |
| 242 | depctl.epdis = 0; |
| 243 | writel(depctl.d32, &ep_reg->depctl); |
| 244 | } |
| 245 | |
| 246 | static void dwc2_halt_ep(struct usbdev_ctrl *this, int ep, int in_dir) |
| 247 | { |
| 248 | dwc2_pdata_t *p = DWC2_PDATA(this); |
| 249 | dwc2_ep_reg_t *ep_reg = p->eps[ep][in_dir].ep_regs; |
| 250 | depctl_t depctl; |
| 251 | dctl_t dctl; |
| 252 | gintsts_t gintsts; |
| 253 | |
| 254 | usb_debug("dwc2_halt_ep ep %d-%d\n", ep, in_dir); |
| 255 | depctl.d32 = readl(&ep_reg->depctl); |
| 256 | /*Alread disabled*/ |
| 257 | if (!depctl.epena) |
| 258 | return; |
| 259 | /* First step: disable EP */ |
| 260 | if (in_dir) { |
| 261 | /* Only support Non-Periodic IN Endpoints */ |
| 262 | dctl.d32 = readl(&p->regs->device.dctl); |
| 263 | dctl.sgnpinnak = 1; |
| 264 | writel(dctl.d32, &p->regs->device.dctl); |
| 265 | |
| 266 | /* Wait for the GINTSTS.Global IN NP NAK Effective interrupt */ |
| 267 | do { |
| 268 | gintsts.d32 = readl(&p->regs->core.gintsts); |
| 269 | } while (!gintsts.ginnakeff); |
| 270 | |
| 271 | /* Clear GINTSTS.Global IN NP NAK Effective interrupt */ |
| 272 | writel(gintsts.d32, &p->regs->core.gintsts); |
| 273 | dwc2_disable_ep(ep_reg); |
| 274 | |
| 275 | /* Flush Tx Fifo */ |
| 276 | dwc2_tx_fifo_flush(this, p->eps[ep][in_dir].txfifo); |
| 277 | |
| 278 | } else { |
| 279 | /* Enable Global OUT NAK mode */ |
| 280 | dctl.d32 = readl(&p->regs->device.dctl); |
| 281 | dctl.sgoutnak = 1; |
| 282 | writel(dctl.d32, &p->regs->device.dctl); |
| 283 | |
| 284 | /* Wait for the GINTSTS.GOUTNakEff interrupt */ |
| 285 | do { |
| 286 | gintsts.d32 = readl(&p->regs->core.gintsts); |
| 287 | } while (!gintsts.goutnakeff); |
| 288 | |
| 289 | /* Clear GINTSTS.GOUTNakEff */ |
| 290 | writel(gintsts.d32, &p->regs->core.gintsts); |
| 291 | |
| 292 | dwc2_disable_ep(ep_reg); |
| 293 | |
| 294 | dctl.d32 = readl(&p->regs->device.dctl); |
| 295 | dctl.cgoutnak = 1; |
| 296 | dctl.sgoutnak = 0; |
| 297 | writel(dctl.d32, &p->regs->device.dctl); |
| 298 | } |
| 299 | |
| 300 | /* Second step: clear job queue */ |
| 301 | while (!SIMPLEQ_EMPTY(&p->eps[ep][in_dir].job_queue)) { |
| 302 | struct job *job = SIMPLEQ_FIRST(&p->eps[ep][in_dir].job_queue); |
| 303 | |
| 304 | if (job->autofree) |
| 305 | free(job->data); |
| 306 | |
| 307 | SIMPLEQ_REMOVE_HEAD(&p->eps[ep][in_dir].job_queue, queue); |
| 308 | } |
| 309 | } |
| 310 | |
| 311 | static int find_tx_fifo(struct usbdev_ctrl *this, uint32_t mps) |
| 312 | { |
| 313 | dwc2_pdata_t *p = DWC2_PDATA(this); |
| 314 | uint32_t fifo_index = 0; |
| 315 | uint32_t fifo_size = UINT_MAX; |
Patrick Georgi | 564fbbe | 2015-10-26 19:48:25 +0100 | [diff] [blame] | 316 | gtxfsiz_t gtxfsiz; |
huang lin | 41e2499 | 2015-05-20 17:27:10 +0800 | [diff] [blame] | 317 | int i, val; |
| 318 | |
| 319 | for (i = 1; i < MAX_EPS_CHANNELS - 1; i++) { |
| 320 | if (p->fifo_map & (1<<i)) |
| 321 | continue; |
Patrick Georgi | 564fbbe | 2015-10-26 19:48:25 +0100 | [diff] [blame] | 322 | gtxfsiz.d32 = readl(&p->regs->core.dptxfsiz_dieptxf[i]); |
| 323 | val = gtxfsiz.txfdep * 4; |
huang lin | 41e2499 | 2015-05-20 17:27:10 +0800 | [diff] [blame] | 324 | |
| 325 | if (val < mps) |
| 326 | continue; |
| 327 | /* Search for smallest acceptable fifo */ |
| 328 | if (val < fifo_size) { |
| 329 | fifo_size = val; |
| 330 | fifo_index = i; |
| 331 | } |
| 332 | } |
| 333 | |
| 334 | if (!fifo_index) |
| 335 | fatal("find_tx_fifo no suitable fifo found\n"); |
| 336 | |
| 337 | p->fifo_map |= 1 << fifo_index; |
| 338 | |
| 339 | return fifo_index; |
| 340 | |
| 341 | } |
| 342 | |
| 343 | static void dwc2_start_ep0(struct usbdev_ctrl *this) |
| 344 | { |
| 345 | dwc2_pdata_t *p = DWC2_PDATA(this); |
| 346 | depctl_t depctl = { .d32 = 0 }; |
| 347 | depint_t depint = { .d32 = 0xff }; |
| 348 | |
| 349 | usb_debug("dwc2_start_ep0\n"); |
| 350 | |
| 351 | /* Enable endpoint, reset data toggle */ |
| 352 | depctl.mps = 0; |
| 353 | depctl.usbactep = 1; |
| 354 | depctl.snak = 1; |
| 355 | depctl.epdis = 1; |
| 356 | |
| 357 | writel(depctl.d32, &p->regs->device.inep[0].depctl); |
| 358 | writel(depint.d32, &p->regs->device.inep[0].depint); |
| 359 | writel(depctl.d32, &p->regs->device.outep[0].depctl); |
| 360 | writel(depint.d32, &p->regs->device.outep[0].depint); |
| 361 | |
| 362 | p->eps[0][0].busy = 0; |
| 363 | p->eps[0][1].busy = 0; |
| 364 | this->ep_mps[0][0] = 64; |
| 365 | this->ep_mps[0][1] = 64; |
| 366 | } |
| 367 | |
| 368 | static void dwc2_start_ep(struct usbdev_ctrl *this, |
| 369 | int ep, int in_dir, int ep_type, int mps) |
| 370 | { |
| 371 | dwc2_pdata_t *p = DWC2_PDATA(this); |
| 372 | dwc2_ep_reg_t *ep_reg = p->eps[ep][in_dir].ep_regs; |
| 373 | depctl_t depctl = { .d32 = 0 }; |
| 374 | |
| 375 | assert((ep < 16) && (ep > 0)); |
| 376 | usb_debug("dwc2_start_ep %d-%d (type %d)\n", ep, in_dir, ep_type); |
| 377 | |
| 378 | in_dir = in_dir ? 1 : 0; |
| 379 | |
| 380 | /* Enable endpoint, reset data toggle */ |
| 381 | depctl.setd0pid = 1; |
| 382 | depctl.mps = mps & 0x3ff; |
| 383 | depctl.usbactep = 1; |
| 384 | |
| 385 | /* ep type 0:ctrl 1:isoc 2:bulk 3:intr */ |
| 386 | depctl.eptype = ep_type; |
| 387 | depctl.snak = 1; |
| 388 | if (in_dir) { |
| 389 | /* Allocate Tx FIFO */ |
| 390 | p->eps[ep][in_dir].txfifo = find_tx_fifo(this, mps); |
| 391 | } |
| 392 | writel(depctl.d32, &ep_reg->depctl); |
| 393 | |
| 394 | p->eps[ep][in_dir].busy = 0; |
| 395 | this->ep_mps[ep][in_dir] = mps; |
| 396 | } |
| 397 | |
| 398 | static void continue_ep_transfer(dwc2_pdata_t *p, |
| 399 | int endpoint, int in_dir) |
| 400 | { |
| 401 | int max_transfer_size = (endpoint == 0) ? EP0_MAXLEN : EP_MAXLEN; |
| 402 | int mps; |
| 403 | uint32_t remind_length; |
| 404 | void *data_buf; |
| 405 | |
| 406 | if (SIMPLEQ_EMPTY(&p->eps[endpoint][in_dir].job_queue)) |
| 407 | return; |
| 408 | |
| 409 | struct job *job = SIMPLEQ_FIRST(&p->eps[endpoint][in_dir].job_queue); |
| 410 | |
| 411 | remind_length = job->length - job->xfered_length; |
| 412 | |
| 413 | job->xfer_length = (remind_length > max_transfer_size) ? |
| 414 | max_transfer_size : remind_length; |
| 415 | data_buf = job->data + job->xfered_length; |
| 416 | |
| 417 | if ((((uint32_t)data_buf & 3) != 0) && (job->xfer_length > 0)) |
| 418 | usb_debug("Un-aligned buffer address\n"); |
| 419 | |
| 420 | if (in_dir) { |
| 421 | dwc2_write_ep(&p->eps[endpoint][in_dir], |
| 422 | job->xfer_length, data_buf); |
| 423 | } else { |
| 424 | mps = get_mps(&p->eps[endpoint][in_dir]); |
| 425 | job->xfer_length = ALIGN_UP(job->xfer_length, mps); |
| 426 | dwc2_read_ep(&p->eps[endpoint][0], job->xfer_length, data_buf); |
| 427 | } |
| 428 | } |
| 429 | |
| 430 | static void start_ep_transfer(dwc2_pdata_t *p, |
| 431 | int endpoint, int in_dir) |
| 432 | { |
| 433 | int max_transfer_size = (endpoint == 0) ? EP0_MAXLEN : EP_MAXLEN; |
| 434 | int mps; |
| 435 | |
| 436 | if (p->eps[endpoint][in_dir].busy) { |
| 437 | usb_debug("ep %d-%d busy\n", endpoint, in_dir); |
| 438 | return; |
| 439 | } |
| 440 | |
| 441 | if (SIMPLEQ_EMPTY(&p->eps[endpoint][in_dir].job_queue)) { |
| 442 | usb_debug("ep %d-%d empty\n", endpoint, in_dir); |
| 443 | return; |
| 444 | } |
| 445 | |
| 446 | struct job *job = SIMPLEQ_FIRST(&p->eps[endpoint][in_dir].job_queue); |
| 447 | |
| 448 | job->xfer_length = (job->length > max_transfer_size) ? |
| 449 | max_transfer_size : job->length; |
| 450 | |
| 451 | if (in_dir) { |
| 452 | dwc2_write_ep(&p->eps[endpoint][1], job->xfer_length, job->data); |
| 453 | } else { |
| 454 | mps = get_mps(&p->eps[endpoint][0]); |
| 455 | job->xfer_length = ALIGN_UP(job->xfer_length, mps); |
| 456 | /* BUG */ |
| 457 | if ((endpoint == 0) && (job->length == 0)) |
| 458 | job->data = p->setup_buf; |
| 459 | dwc2_read_ep(&p->eps[endpoint][0], job->xfer_length, job->data); |
| 460 | } |
| 461 | |
| 462 | usb_debug("start EP %d-%d with %zx bytes starting at %p\n", endpoint, |
| 463 | in_dir, job->length, job->data); |
| 464 | |
| 465 | p->eps[endpoint][in_dir].busy = 1; |
| 466 | } |
| 467 | |
| 468 | static void dwc2_enqueue_packet(struct usbdev_ctrl *this, int endpoint, |
| 469 | int in_dir, void *data, int len, int zlp, int autofree) |
| 470 | { |
| 471 | dwc2_pdata_t *p = DWC2_PDATA(this); |
| 472 | struct job *job = xzalloc(sizeof(*job)); |
| 473 | |
| 474 | job->data = data; |
| 475 | job->length = len; |
| 476 | job->zlp = zlp; |
| 477 | job->autofree = autofree; |
| 478 | |
| 479 | usb_debug("adding job %d bytes to EP %d-%d\n", len, endpoint, in_dir); |
| 480 | SIMPLEQ_INSERT_TAIL(&p->eps[endpoint][in_dir].job_queue, job, queue); |
| 481 | |
| 482 | if ((endpoint == 0) || (this->initialized)) |
| 483 | start_ep_transfer(p, endpoint, in_dir); |
| 484 | } |
| 485 | |
| 486 | static void complete_ep_transfer(struct usbdev_ctrl *this, int endpoint, |
| 487 | int in_dir, int xfer_result) |
| 488 | { |
| 489 | dwc2_pdata_t *p = DWC2_PDATA(this); |
| 490 | struct job *job = SIMPLEQ_FIRST(&p->eps[endpoint][in_dir].job_queue); |
| 491 | int mps = this->ep_mps[endpoint][in_dir]; |
| 492 | |
| 493 | if (in_dir) { |
| 494 | job->xfered_length += job->xfer_length - xfer_result; |
| 495 | if (job->xfered_length < job->length || |
| 496 | (job->xfered_length == job->length && |
| 497 | job->xfered_length % mps == 0 && job->xfer_length)) { |
| 498 | continue_ep_transfer(p, endpoint, in_dir); |
| 499 | return; |
| 500 | } |
| 501 | } else { |
| 502 | job->xfered_length += job->xfer_length - xfer_result; |
| 503 | } |
| 504 | SIMPLEQ_REMOVE_HEAD(&p->eps[endpoint][in_dir].job_queue, queue); |
| 505 | |
| 506 | usb_debug("%d-%d: scheduled %zd, now %d bytes\n", endpoint, in_dir, |
| 507 | job->length, job->xfered_length); |
| 508 | |
| 509 | if (this->current_config && |
| 510 | this->current_config->interfaces[0].handle_packet) |
| 511 | this->current_config->interfaces[0].handle_packet(this, |
| 512 | endpoint, in_dir, job->data, job->xfered_length); |
| 513 | |
| 514 | if (job->autofree) |
| 515 | free(job->data); |
| 516 | free(job); |
| 517 | |
| 518 | p->eps[endpoint][in_dir].busy = 0; |
| 519 | |
| 520 | if (endpoint == 0 && job->xfered_length == 0) |
| 521 | dwc2_enqueue_packet(this, 0, 0, p->setup_buf, 8, 0, 0); |
Patrick Georgi | 102245f | 2015-10-26 19:48:25 +0100 | [diff] [blame] | 522 | else |
| 523 | start_ep_transfer(p, endpoint, in_dir); |
huang lin | 41e2499 | 2015-05-20 17:27:10 +0800 | [diff] [blame] | 524 | } |
| 525 | |
| 526 | static void dwc2_outep_intr(struct usbdev_ctrl *this, dwc2_ep_t *ep) |
| 527 | { |
| 528 | dwc2_pdata_t *p = DWC2_PDATA(this); |
| 529 | depint_t depint; |
| 530 | depsiz_t depsiz; |
| 531 | |
| 532 | depint.d32 = readl(&ep->ep_regs->depint) & |
| 533 | readl(&p->regs->device.doepmsk); |
| 534 | |
| 535 | /* Don't process XferCompl interrupt if it is a setup packet */ |
| 536 | if ((ep->ep_num == 0) && (depint.setup || depint.stuppktrcvd)) |
| 537 | depint.xfercompl = 0; |
| 538 | |
| 539 | /* Transfer completed */ |
| 540 | if (depint.xfercompl) { |
| 541 | usb_debug("DOEPINT_XFERCOMPL\n"); |
| 542 | writel(DXEPINT_XFERCOMPL, &ep->ep_regs->depint); |
| 543 | depsiz.d32 = readl(&ep->ep_regs->deptsiz); |
| 544 | |
| 545 | if (ep->ep_num == 0) |
| 546 | depsiz.xfersize &= 0x7f; |
| 547 | |
| 548 | complete_ep_transfer(this, ep->ep_num, 0, depsiz.xfersize); |
| 549 | } |
| 550 | /* Endpoint disable */ |
| 551 | if (depint.epdisbld) { |
| 552 | usb_debug("DEPINT_EPDISBLD\n"); |
| 553 | writel(DXEPINT_EPDISBLD, &ep->ep_regs->depint); |
| 554 | } |
| 555 | /* AHB Error */ |
| 556 | if (depint.ahberr) { |
| 557 | usb_debug("DEPINT_AHBERR\n"); |
| 558 | writel(DXEPINT_AHBERR, &ep->ep_regs->depint); |
| 559 | } |
| 560 | |
| 561 | /* Handle Setup Phase Done (Contorl Ep) */ |
| 562 | if (depint.setup) { |
| 563 | usb_debug("DEPINT_SETUP\n"); |
| 564 | writel(DXEPINT_SETUP, &ep->ep_regs->depint); |
| 565 | #ifdef USB_DEBUG |
Patrick Georgi | b791799 | 2015-10-26 19:48:25 +0100 | [diff] [blame] | 566 | hexdump(p->setup_buf, sizeof(dev_req_t)); |
huang lin | 41e2499 | 2015-05-20 17:27:10 +0800 | [diff] [blame] | 567 | #endif |
| 568 | SIMPLEQ_REMOVE_HEAD(&p->eps[0][0].job_queue, queue); |
| 569 | p->eps[0][0].busy = 0; |
| 570 | |
| 571 | udc_handle_setup(this, ep->ep_num, (dev_req_t *)p->setup_buf); |
| 572 | } |
| 573 | } |
| 574 | |
| 575 | static void dwc2_inep_intr(struct usbdev_ctrl *this, dwc2_ep_t *ep) |
| 576 | { |
| 577 | dwc2_pdata_t *p = DWC2_PDATA(this); |
| 578 | depint_t depint; |
| 579 | depsiz_t depsiz; |
| 580 | |
| 581 | depint.d32 = readl(&ep->ep_regs->depint) & |
| 582 | readl(&p->regs->device.doepmsk); |
| 583 | |
| 584 | /* Don't process XferCompl interrupt if it is a setup packet */ |
| 585 | if ((ep->ep_num == 0) && (depint.setup)) { |
| 586 | usb_debug("IN ep timeout\n"); |
| 587 | writel(DXEPINT_TIMEOUT, &ep->ep_regs->depint); |
| 588 | } |
| 589 | |
| 590 | /* Transfer completed */ |
| 591 | if (depint.xfercompl) { |
| 592 | usb_debug("DIEPINT_XFERCOMPL\n"); |
| 593 | writel(DXEPINT_XFERCOMPL, &ep->ep_regs->depint); |
| 594 | depsiz.d32 = readl(&ep->ep_regs->deptsiz); |
| 595 | |
| 596 | if (ep->ep_num == 0) |
| 597 | depsiz.xfersize &= 0x7f; |
| 598 | |
| 599 | complete_ep_transfer(this, ep->ep_num, 1, depsiz.xfersize); |
| 600 | } |
| 601 | /* Endpoint disable */ |
| 602 | if (depint.epdisbld) { |
| 603 | usb_debug("DEPINT_EPDISBLD\n"); |
| 604 | writel(DXEPINT_EPDISBLD, &ep->ep_regs->depint); |
| 605 | } |
| 606 | /* AHB Error */ |
| 607 | if (depint.ahberr) { |
| 608 | usb_debug("DEPINT_AHBERR\n"); |
| 609 | writel(DXEPINT_AHBERR, &ep->ep_regs->depint); |
| 610 | } |
| 611 | } |
| 612 | |
| 613 | static int dwc2_check_irq(struct usbdev_ctrl *this) |
| 614 | { |
| 615 | dwc2_pdata_t *p = DWC2_PDATA(this); |
| 616 | gintsts_t gintsts; |
| 617 | uint32_t daint, daint_out, daint_in, ep; |
| 618 | |
| 619 | gintsts.d32 = readl(&p->regs->core.gintsts) & |
| 620 | readl(&p->regs->core.gintmsk); |
| 621 | |
| 622 | if (gintsts.d32 == 0) |
| 623 | return 1; |
| 624 | |
| 625 | /* EP INTR */ |
| 626 | if (gintsts.oepint || gintsts.iepint) { |
| 627 | |
| 628 | daint = readl(&p->regs->device.daint) & |
| 629 | readl(&p->regs->device.daintmsk); |
| 630 | |
| 631 | daint_out = daint >> DAINT_OUTEP_SHIFT; |
| 632 | daint_in = daint & ~(daint_out << DAINT_OUTEP_SHIFT); |
| 633 | |
| 634 | for (ep = 0; ep < MAX_EPS_CHANNELS; ep++, daint_in >>= 1) { |
| 635 | if (daint_in & 1) |
| 636 | dwc2_inep_intr(this, &p->eps[ep][1]); |
| 637 | } |
| 638 | |
| 639 | for (ep = 0; ep < MAX_EPS_CHANNELS; ep++, daint_out >>= 1) { |
| 640 | if (daint_out & 1) |
| 641 | dwc2_outep_intr(this, &p->eps[ep][0]); |
| 642 | } |
| 643 | } |
| 644 | |
| 645 | /* USB Bus Suspend */ |
| 646 | if (gintsts.usbsusp) { |
| 647 | usb_debug("GINTSTS_ERLYSUSP\n"); |
| 648 | writel(GINTSTS_USBSUSP, &p->regs->core.gintsts); |
| 649 | } |
| 650 | /* USB Bus Reset */ |
| 651 | if (gintsts.usbrst) { |
| 652 | usb_debug("GINTSTS_USBRST\n"); |
| 653 | dwc2_bus_reset(this); |
| 654 | writel(GINTSTS_USBRST, &p->regs->core.gintsts); |
| 655 | } |
| 656 | /* Enumeration done */ |
| 657 | if (gintsts.enumdone) { |
| 658 | usb_debug("GINTSTS_ENUMDONE\n"); |
| 659 | dwc2_enum_done(this); |
| 660 | writel(GINTSTS_ENUMDONE, &p->regs->core.gintsts); |
| 661 | } |
| 662 | if (gintsts.sessreqint) { |
| 663 | usb_debug("GINTSTS_SESSREQINT\n"); |
| 664 | writel(GINTSTS_SESSREQINT, &p->regs->core.gintsts); |
| 665 | } |
| 666 | if (gintsts.wkupint) { |
| 667 | usb_debug("GINTSTS_WKUPINT\n"); |
| 668 | writel(GINTSTS_WKUPINT, &p->regs->core.gintsts); |
| 669 | } |
| 670 | |
| 671 | return 1; |
| 672 | } |
| 673 | |
Yunzhi Li | d8a3ed4 | 2015-06-23 17:42:34 +0800 | [diff] [blame] | 674 | static void dwc2_force_shutdown(struct usbdev_ctrl *this) |
huang lin | 41e2499 | 2015-05-20 17:27:10 +0800 | [diff] [blame] | 675 | { |
huang lin | 41e2499 | 2015-05-20 17:27:10 +0800 | [diff] [blame] | 676 | gusbcfg_t gusbcfg; |
Yunzhi Li | d8a3ed4 | 2015-06-23 17:42:34 +0800 | [diff] [blame] | 677 | dwc2_pdata_t *p = DWC2_PDATA(this); |
huang lin | 41e2499 | 2015-05-20 17:27:10 +0800 | [diff] [blame] | 678 | |
| 679 | /* Disconnect */ |
| 680 | dwc2_connect(this, 0); |
| 681 | |
| 682 | /* Back to normal otg mode */ |
| 683 | gusbcfg.d32 = readl(&p->regs->core.gusbcfg); |
| 684 | gusbcfg.forcehstmode = 0; |
| 685 | gusbcfg.forcedevmode = 0; |
| 686 | writel(gusbcfg.d32, &p->regs->core.gusbcfg); |
| 687 | |
| 688 | free(p); |
| 689 | free(this); |
| 690 | } |
| 691 | |
Yunzhi Li | d8a3ed4 | 2015-06-23 17:42:34 +0800 | [diff] [blame] | 692 | static void dwc2_shutdown(struct usbdev_ctrl *this) |
| 693 | { |
| 694 | dwc2_pdata_t *p = DWC2_PDATA(this); |
| 695 | int i, j; |
| 696 | int is_empty = 0; |
| 697 | |
Furquan Shaikh | 3d6c95c | 2015-11-04 16:09:08 -0800 | [diff] [blame] | 698 | uint64_t shutdown_timer_us = timer_us(0); |
| 699 | /* Wait up to 3 seconds for packets to be flushed out. */ |
| 700 | uint64_t shutdown_timeout_us = 3 * 1000 * 1000UL; |
| 701 | |
| 702 | while ((!is_empty) && |
| 703 | (timer_us(shutdown_timer_us) < shutdown_timeout_us)) { |
Yunzhi Li | d8a3ed4 | 2015-06-23 17:42:34 +0800 | [diff] [blame] | 704 | is_empty = 1; |
| 705 | this->poll(this); |
| 706 | for (i = 0; i < 16; i++) |
Furquan Shaikh | fe35623 | 2015-11-06 22:22:56 -0800 | [diff] [blame] | 707 | for (j = 0; j < 2; j++) { |
| 708 | /* |
| 709 | * EP0-OUT needs to always have an active packet |
| 710 | * for proper operation of control packet |
| 711 | * flow. Thus, ignore if only 1 packet is |
| 712 | * present in EP0-OUT. |
| 713 | */ |
| 714 | if ((i == 0) && (j == 0) && |
| 715 | SIMPLEQ_SINGLETON(&p->eps[0][0].job_queue, |
| 716 | queue)) |
| 717 | continue; |
| 718 | |
Yunzhi Li | d8a3ed4 | 2015-06-23 17:42:34 +0800 | [diff] [blame] | 719 | if (!SIMPLEQ_EMPTY(&p->eps[i][j].job_queue)) |
| 720 | is_empty = 0; |
Furquan Shaikh | fe35623 | 2015-11-06 22:22:56 -0800 | [diff] [blame] | 721 | } |
Yunzhi Li | d8a3ed4 | 2015-06-23 17:42:34 +0800 | [diff] [blame] | 722 | } |
| 723 | |
Furquan Shaikh | 3d6c95c | 2015-11-04 16:09:08 -0800 | [diff] [blame] | 724 | if (timer_us(shutdown_timer_us) >= shutdown_timeout_us) |
| 725 | usb_debug("Error: Failed to empty queues.. timeout\n"); |
| 726 | |
Yunzhi Li | d8a3ed4 | 2015-06-23 17:42:34 +0800 | [diff] [blame] | 727 | dwc2_force_shutdown(this); |
| 728 | } |
| 729 | |
huang lin | 41e2499 | 2015-05-20 17:27:10 +0800 | [diff] [blame] | 730 | static void dwc2_set_address(struct usbdev_ctrl *this, int address) |
| 731 | { |
| 732 | dwc2_pdata_t *p = DWC2_PDATA(this); |
| 733 | dcfg_t dcfg; |
| 734 | |
| 735 | dcfg.d32 = readl(&p->regs->device.dcfg); |
| 736 | dcfg.devaddr = address; |
| 737 | writel(dcfg.d32, &p->regs->device.dcfg); |
| 738 | } |
| 739 | |
| 740 | static void dwc2_stall(struct usbdev_ctrl *this, |
| 741 | uint8_t ep, int in_dir, int set) |
| 742 | { |
| 743 | dwc2_pdata_t *p = DWC2_PDATA(this); |
| 744 | dwc2_ep_reg_t *ep_reg = p->eps[ep][in_dir].ep_regs; |
| 745 | depctl_t depctl; |
| 746 | |
| 747 | usb_debug("dwc2_stall\n"); |
| 748 | depctl.d32 = readl(&ep_reg->depctl); |
| 749 | |
| 750 | in_dir = in_dir ? 1 : 0; |
| 751 | |
| 752 | if (set) { |
| 753 | depctl.stall = 1; |
| 754 | depctl.setd0pid = 1; |
| 755 | writel(depctl.d32, &ep_reg->depctl); |
| 756 | } else { |
| 757 | /* STALL bit will be clear by core */ |
| 758 | } |
| 759 | this->ep_halted[ep][in_dir] = set; |
| 760 | } |
| 761 | |
| 762 | static void *dwc2_malloc(size_t size) |
| 763 | { |
| 764 | return dma_memalign(4096, size); |
| 765 | } |
| 766 | |
| 767 | static void dwc2_free(void *ptr) |
| 768 | { |
| 769 | free(ptr); |
| 770 | } |
| 771 | |
| 772 | static int dwc2_reinit_udc(struct usbdev_ctrl *this, void *_opreg, |
| 773 | const device_descriptor_t *dd) |
| 774 | { |
| 775 | grstctl_t grstctl = { .d32 = 0 }; |
| 776 | gintmsk_t gintmsk = { .d32 = 0 }; |
| 777 | gahbcfg_t gahbcfg = { .d32 = 0 }; |
| 778 | gusbcfg_t gusbcfg = { .d32 = 0 }; |
| 779 | grxfsiz_t grxfsiz = { .d32 = 0 }; |
| 780 | dtxfsiz_t dtxfsiz0 = { .d32 = 0 }; |
| 781 | dtxfsiz_t dtxfsiz1 = { .d32 = 0 }; |
| 782 | dtxfsiz_t dtxfsiz2 = { .d32 = 0 }; |
| 783 | depint_t depint_msk = { .d32 = 0 }; |
| 784 | dcfg_t dcfg = { .d32 = 0 }; |
| 785 | dwc2_reg_t *regs = (dwc2_reg_t *)_opreg; |
| 786 | dwc2_pdata_t *p = DWC2_PDATA(this); |
| 787 | const int timeout = 10000; |
| 788 | int i; |
| 789 | |
| 790 | p->regs = phys_to_virt(regs); |
| 791 | p->fifo_map = 0; |
| 792 | p->setup_buf = dma_memalign(4, 64); |
| 793 | |
| 794 | for (i = 0; i < MAX_EPS_CHANNELS; i++) { |
| 795 | /* Init OUT EPs */ |
| 796 | p->eps[i][0].ep_num = i; |
| 797 | p->eps[i][0].ep_regs = ®s->device.outep[i]; |
| 798 | SIMPLEQ_INIT(&p->eps[i][0].job_queue); |
| 799 | |
| 800 | /* Init IN EPs */ |
| 801 | p->eps[i][1].ep_num = i; |
| 802 | p->eps[i][1].ep_regs = ®s->device.inep[i]; |
| 803 | SIMPLEQ_INIT(&p->eps[i][1].job_queue); |
| 804 | } |
| 805 | |
| 806 | usb_debug("dwc2_hw_init\n"); |
| 807 | |
| 808 | /* Wait for AHB idle */ |
| 809 | for (i = 0; i < timeout; i++) { |
| 810 | udelay(1); |
| 811 | grstctl.d32 = readl(®s->core.grstctl); |
| 812 | if (grstctl.ahbidle) |
| 813 | break; |
| 814 | } |
| 815 | if (i == timeout) { |
| 816 | usb_debug("DWC2 Init error AHB Idle\n"); |
| 817 | return 0; |
| 818 | } |
| 819 | |
| 820 | /* Restart the Phy Clock */ |
| 821 | /* Core soft reset */ |
| 822 | grstctl.csftrst = 1; |
| 823 | writel(grstctl.d32, ®s->core.grstctl); |
| 824 | for (i = 0; i <= timeout; i++) { |
| 825 | udelay(1); |
| 826 | grstctl.d32 = readl(®s->core.grstctl); |
| 827 | if (!grstctl.csftrst) |
| 828 | break; |
| 829 | |
| 830 | if (i == timeout) { |
| 831 | usb_debug("DWC2 Init error reset fail\n"); |
| 832 | return 0; |
| 833 | } |
| 834 | } |
| 835 | |
| 836 | /* Restart the Phy Clock */ |
| 837 | writel(0x0, ®s->pcgr.pcgcctl); |
| 838 | |
| 839 | /* Set 16bit PHY if & Force host mode */ |
| 840 | gusbcfg.d32 = readl(®s->core.gusbcfg); |
| 841 | gusbcfg.phyif = 1; |
| 842 | gusbcfg.forcehstmode = 0; |
| 843 | gusbcfg.forcedevmode = 1; |
| 844 | writel(gusbcfg.d32, ®s->core.gusbcfg); |
| 845 | |
| 846 | dcfg.d32 = readl(®s->device.dcfg); |
| 847 | /* reset device addr */ |
| 848 | dcfg.devaddr = 0; |
| 849 | /* enable HS */ |
| 850 | dcfg.devspd = 0; |
| 851 | writel(dcfg.d32, ®s->device.dcfg); |
| 852 | |
| 853 | dwc2_tx_fifo_flush(this, 0x10); |
| 854 | dwc2_rx_fifo_flush(this, 0); |
| 855 | |
| 856 | grxfsiz.rxfdep = RX_FIFO_SIZE; |
| 857 | writel(grxfsiz.d32, ®s->core.grxfsiz); |
| 858 | |
| 859 | dtxfsiz0.dtxfdep = DTX_FIFO_SIZE_0; |
| 860 | dtxfsiz0.dtxfstaddr = DTX_FIFO_SIZE_0_OFFSET; |
| 861 | writel(dtxfsiz0.d32, ®s->core.gnptxfsiz); |
| 862 | |
| 863 | dtxfsiz1.dtxfdep = DTX_FIFO_SIZE_1; |
| 864 | dtxfsiz1.dtxfstaddr = DTX_FIFO_SIZE_1_OFFSET; |
| 865 | writel(dtxfsiz1.d32, ®s->core.dptxfsiz_dieptxf[0]); |
| 866 | |
| 867 | dtxfsiz2.dtxfdep = DTX_FIFO_SIZE_2; |
| 868 | dtxfsiz2.dtxfstaddr = DTX_FIFO_SIZE_2_OFFSET; |
| 869 | writel(dtxfsiz2.d32, ®s->core.dptxfsiz_dieptxf[1]); |
| 870 | |
| 871 | /* Config Ep0 */ |
| 872 | dwc2_start_ep0(this); |
| 873 | |
| 874 | dwc2_enqueue_packet(this, 0, 0, p->setup_buf, 8, 0, 0); |
| 875 | |
| 876 | depint_msk.xfercompl = 1; |
| 877 | depint_msk.epdisbld = 1; |
| 878 | depint_msk.ahberr = 1; |
| 879 | depint_msk.setup = 1; |
| 880 | |
| 881 | /* device IN interrupt mask */ |
| 882 | writel(depint_msk.d32, ®s->device.diepmsk); |
| 883 | /* device OUT interrupt mask */ |
| 884 | writel(depint_msk.d32, ®s->device.doepmsk); |
| 885 | |
| 886 | /* Clear all pending interrupt */ |
| 887 | writel(0xffffffff, ®s->device.daint); |
| 888 | |
| 889 | /* Config core interface regs */ |
| 890 | writel(0xffffffff, ®s->core.gintsts); |
| 891 | writel(0xffffffff, ®s->core.gotgint); |
| 892 | |
| 893 | /* Enable device endpoint interrupt */ |
| 894 | writel(0xffffffff, ®s->device.daintmsk); |
| 895 | |
| 896 | gintmsk.usbsusp = 1; |
| 897 | gintmsk.usbrst = 1; |
| 898 | gintmsk.enumdone = 1; |
| 899 | gintmsk.sessreqint = 1; |
| 900 | gintmsk.iepint = 1; |
| 901 | gintmsk.oepint = 1; |
| 902 | writel(gintmsk.d32, ®s->core.gintmsk); |
| 903 | |
| 904 | gahbcfg.d32 = readl(®s->core.gahbcfg); |
| 905 | gahbcfg.dmaen = 1; |
| 906 | gahbcfg.glblintrmsk = 1; |
| 907 | gahbcfg.hbstlen = DMA_BURST_INCR16; |
| 908 | writel(gahbcfg.d32, ®s->core.gahbcfg); |
| 909 | |
| 910 | dwc2_connect(this, 1); |
| 911 | |
| 912 | return 1; |
| 913 | |
| 914 | } |
| 915 | |
| 916 | struct usbdev_ctrl *dwc2_udc_init(device_descriptor_t *dd) |
| 917 | { |
| 918 | struct usbdev_ctrl *ctrl = calloc(1, sizeof(*ctrl)); |
| 919 | int i; |
| 920 | |
| 921 | usb_debug("dwc2_udc_init\n"); |
| 922 | if (ctrl == NULL) |
| 923 | return NULL; |
| 924 | |
| 925 | ctrl->pdata = calloc(1, sizeof(dwc2_pdata_t)); |
| 926 | if (ctrl->pdata == NULL) { |
| 927 | free(ctrl); |
| 928 | return NULL; |
| 929 | } |
| 930 | memcpy(&ctrl->device_descriptor, dd, sizeof(*dd)); |
| 931 | SLIST_INIT(&ctrl->configs); |
| 932 | |
| 933 | ctrl->poll = dwc2_check_irq; |
| 934 | ctrl->add_gadget = udc_add_gadget; |
Furquan Shaikh | bf54c2c | 2015-11-04 16:11:38 -0800 | [diff] [blame] | 935 | ctrl->add_strings = udc_add_strings; |
huang lin | 41e2499 | 2015-05-20 17:27:10 +0800 | [diff] [blame] | 936 | ctrl->enqueue_packet = dwc2_enqueue_packet; |
Yunzhi Li | d8a3ed4 | 2015-06-23 17:42:34 +0800 | [diff] [blame] | 937 | ctrl->force_shutdown = dwc2_force_shutdown; |
huang lin | 41e2499 | 2015-05-20 17:27:10 +0800 | [diff] [blame] | 938 | ctrl->shutdown = dwc2_shutdown; |
| 939 | ctrl->set_address = dwc2_set_address; |
| 940 | ctrl->stall = dwc2_stall; |
| 941 | ctrl->halt_ep = dwc2_halt_ep; |
| 942 | ctrl->start_ep = dwc2_start_ep; |
| 943 | ctrl->alloc_data = dwc2_malloc; |
| 944 | ctrl->free_data = dwc2_free; |
| 945 | ctrl->initialized = 0; |
| 946 | |
| 947 | ctrl->ep_mps[0][0] = 64; |
| 948 | ctrl->ep_mps[0][1] = 64; |
| 949 | for (i = 1; i < 16; i++) { |
| 950 | ctrl->ep_mps[i][0] = 512; |
| 951 | ctrl->ep_mps[i][1] = 512; |
| 952 | } |
| 953 | |
| 954 | if (!dwc2_reinit_udc(ctrl, (void *)0xff580000, dd)) { |
| 955 | free(ctrl->pdata); |
| 956 | free(ctrl); |
| 957 | return NULL; |
| 958 | } |
| 959 | |
| 960 | return ctrl; |
| 961 | } |
| 962 | |