David Hendricks | 2fba5e2 | 2013-03-14 19:06:11 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright 2013 Google Inc. |
| 5 | * |
| 6 | * Redistribution and use in source and binary forms, with or without |
| 7 | * modification, are permitted provided that the following conditions |
| 8 | * are met: |
| 9 | * 1. Redistributions of source code must retain the above copyright |
| 10 | * notice, this list of conditions and the following disclaimer. |
| 11 | * 2. Redistributions in binary form must reproduce the above copyright |
| 12 | * notice, this list of conditions and the following disclaimer in the |
| 13 | * documentation and/or other materials provided with the distribution. |
| 14 | * 3. The name of the author may not be used to endorse or promote products |
| 15 | * derived from this software without specific prior written permission. |
| 16 | * |
| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
| 18 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 19 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 20 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
| 21 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| 22 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
| 23 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
| 24 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
| 25 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
| 26 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
| 27 | * SUCH DAMAGE. |
| 28 | * |
David Hendricks | 08e3656 | 2013-03-25 15:02:29 -0700 | [diff] [blame] | 29 | * cache.c: Cache maintenance routines for ARMv7-A and ARMv7-R |
| 30 | * |
| 31 | * Reference: ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition |
David Hendricks | 2fba5e2 | 2013-03-14 19:06:11 -0700 | [diff] [blame] | 32 | */ |
| 33 | |
David Hendricks | 6119bea | 2013-03-29 13:24:29 -0700 | [diff] [blame] | 34 | #include <stdint.h> |
David Hendricks | 2fba5e2 | 2013-03-14 19:06:11 -0700 | [diff] [blame] | 35 | |
| 36 | #include <arch/cache.h> |
Julius Werner | f09f224 | 2013-08-28 14:43:14 -0700 | [diff] [blame] | 37 | #include <arch/virtual.h> |
David Hendricks | 2fba5e2 | 2013-03-14 19:06:11 -0700 | [diff] [blame] | 38 | |
David Hendricks | 2fba5e2 | 2013-03-14 19:06:11 -0700 | [diff] [blame] | 39 | void tlb_invalidate_all(void) |
| 40 | { |
Julius Werner | fd9defc | 2014-01-21 20:11:22 -0800 | [diff] [blame] | 41 | /* TLBIALL includes dTLB and iTLB on systems that have them. */ |
David Hendricks | 2fba5e2 | 2013-03-14 19:06:11 -0700 | [diff] [blame] | 42 | tlbiall(); |
David Hendricks | 2fba5e2 | 2013-03-14 19:06:11 -0700 | [diff] [blame] | 43 | dsb(); |
David Hendricks | 2fba5e2 | 2013-03-14 19:06:11 -0700 | [diff] [blame] | 44 | isb(); |
| 45 | } |
| 46 | |
| 47 | enum dcache_op { |
David Hendricks | b98ab4a | 2013-08-16 12:17:50 -0700 | [diff] [blame] | 48 | OP_DCCSW, |
David Hendricks | 2fba5e2 | 2013-03-14 19:06:11 -0700 | [diff] [blame] | 49 | OP_DCCISW, |
David Hendricks | 08e3656 | 2013-03-25 15:02:29 -0700 | [diff] [blame] | 50 | OP_DCISW, |
| 51 | OP_DCCIMVAC, |
| 52 | OP_DCCMVAC, |
Hung-Te Lin | cb0aeef | 2013-07-08 12:27:13 +0800 | [diff] [blame] | 53 | OP_DCIMVAC, |
David Hendricks | 2fba5e2 | 2013-03-14 19:06:11 -0700 | [diff] [blame] | 54 | }; |
| 55 | |
Gabe Black | d40be11 | 2013-10-09 23:45:07 -0700 | [diff] [blame] | 56 | unsigned int dcache_line_bytes(void) |
David Hendricks | 2fba5e2 | 2013-03-14 19:06:11 -0700 | [diff] [blame] | 57 | { |
| 58 | uint32_t ccsidr; |
Gabe Black | d40be11 | 2013-10-09 23:45:07 -0700 | [diff] [blame] | 59 | static unsigned int line_bytes = 0; |
| 60 | |
| 61 | if (line_bytes) |
| 62 | return line_bytes; |
David Hendricks | 2fba5e2 | 2013-03-14 19:06:11 -0700 | [diff] [blame] | 63 | |
| 64 | ccsidr = read_ccsidr(); |
| 65 | /* [2:0] - Indicates (Log2(number of words in cache line)) - 2 */ |
Gabe Black | d40be11 | 2013-10-09 23:45:07 -0700 | [diff] [blame] | 66 | line_bytes = 1 << ((ccsidr & 0x7) + 2); /* words per line */ |
| 67 | line_bytes *= sizeof(unsigned int); /* bytes per line */ |
David Hendricks | 2fba5e2 | 2013-03-14 19:06:11 -0700 | [diff] [blame] | 68 | |
Gabe Black | d40be11 | 2013-10-09 23:45:07 -0700 | [diff] [blame] | 69 | return line_bytes; |
David Hendricks | 2fba5e2 | 2013-03-14 19:06:11 -0700 | [diff] [blame] | 70 | } |
| 71 | |
David Hendricks | 08e3656 | 2013-03-25 15:02:29 -0700 | [diff] [blame] | 72 | /* |
| 73 | * Do a dcache operation by modified virtual address. This is useful for |
| 74 | * maintaining coherency in drivers which do DMA transfers and only need to |
| 75 | * perform cache maintenance on a particular memory range rather than the |
| 76 | * entire cache. |
| 77 | */ |
Julius Werner | f09f224 | 2013-08-28 14:43:14 -0700 | [diff] [blame] | 78 | static void dcache_op_mva(void const *vaddr, size_t len, enum dcache_op op) |
David Hendricks | 2fba5e2 | 2013-03-14 19:06:11 -0700 | [diff] [blame] | 79 | { |
David Hendricks | 08e3656 | 2013-03-25 15:02:29 -0700 | [diff] [blame] | 80 | unsigned long line, linesize; |
Julius Werner | f09f224 | 2013-08-28 14:43:14 -0700 | [diff] [blame] | 81 | unsigned long paddr = virt_to_phys(vaddr); |
David Hendricks | 2fba5e2 | 2013-03-14 19:06:11 -0700 | [diff] [blame] | 82 | |
Gabe Black | d40be11 | 2013-10-09 23:45:07 -0700 | [diff] [blame] | 83 | linesize = dcache_line_bytes(); |
Julius Werner | f09f224 | 2013-08-28 14:43:14 -0700 | [diff] [blame] | 84 | line = paddr & ~(linesize - 1); |
David Hendricks | 08e3656 | 2013-03-25 15:02:29 -0700 | [diff] [blame] | 85 | |
| 86 | dsb(); |
Julius Werner | f09f224 | 2013-08-28 14:43:14 -0700 | [diff] [blame] | 87 | while (line < paddr + len) { |
David Hendricks | 08e3656 | 2013-03-25 15:02:29 -0700 | [diff] [blame] | 88 | switch(op) { |
| 89 | case OP_DCCIMVAC: |
| 90 | dccimvac(line); |
| 91 | break; |
Hung-Te Lin | d0fa1d1 | 2013-07-08 12:25:34 +0800 | [diff] [blame] | 92 | case OP_DCCMVAC: |
| 93 | dccmvac(line); |
| 94 | break; |
Hung-Te Lin | cb0aeef | 2013-07-08 12:27:13 +0800 | [diff] [blame] | 95 | case OP_DCIMVAC: |
| 96 | dcimvac(line); |
| 97 | break; |
David Hendricks | 08e3656 | 2013-03-25 15:02:29 -0700 | [diff] [blame] | 98 | default: |
| 99 | break; |
| 100 | } |
| 101 | line += linesize; |
| 102 | } |
| 103 | isb(); |
David Hendricks | 2fba5e2 | 2013-03-14 19:06:11 -0700 | [diff] [blame] | 104 | } |
| 105 | |
Julius Werner | f09f224 | 2013-08-28 14:43:14 -0700 | [diff] [blame] | 106 | void dcache_clean_by_mva(void const *addr, size_t len) |
David Hendricks | 2fba5e2 | 2013-03-14 19:06:11 -0700 | [diff] [blame] | 107 | { |
David Hendricks | 08e3656 | 2013-03-25 15:02:29 -0700 | [diff] [blame] | 108 | dcache_op_mva(addr, len, OP_DCCMVAC); |
| 109 | } |
| 110 | |
Julius Werner | f09f224 | 2013-08-28 14:43:14 -0700 | [diff] [blame] | 111 | void dcache_clean_invalidate_by_mva(void const *addr, size_t len) |
David Hendricks | 08e3656 | 2013-03-25 15:02:29 -0700 | [diff] [blame] | 112 | { |
| 113 | dcache_op_mva(addr, len, OP_DCCIMVAC); |
| 114 | } |
| 115 | |
Julius Werner | f09f224 | 2013-08-28 14:43:14 -0700 | [diff] [blame] | 116 | void dcache_invalidate_by_mva(void const *addr, size_t len) |
Hung-Te Lin | cb0aeef | 2013-07-08 12:27:13 +0800 | [diff] [blame] | 117 | { |
| 118 | dcache_op_mva(addr, len, OP_DCIMVAC); |
| 119 | } |
| 120 | |
Julius Werner | fd9defc | 2014-01-21 20:11:22 -0800 | [diff] [blame] | 121 | /* |
| 122 | * CAUTION: This implementation assumes that coreboot never uses non-identity |
| 123 | * page tables for pages containing executed code. If you ever want to violate |
| 124 | * this assumption, have fun figuring out the associated problems on your own. |
| 125 | */ |
David Hendricks | 08e3656 | 2013-03-25 15:02:29 -0700 | [diff] [blame] | 126 | void dcache_mmu_disable(void) |
| 127 | { |
David Hendricks | 6119bea | 2013-03-29 13:24:29 -0700 | [diff] [blame] | 128 | uint32_t sctlr; |
David Hendricks | 08e3656 | 2013-03-25 15:02:29 -0700 | [diff] [blame] | 129 | |
| 130 | dcache_clean_invalidate_all(); |
David Hendricks | 08e3656 | 2013-03-25 15:02:29 -0700 | [diff] [blame] | 131 | sctlr = read_sctlr(); |
| 132 | sctlr &= ~(SCTLR_C | SCTLR_M); |
| 133 | write_sctlr(sctlr); |
| 134 | } |
| 135 | |
David Hendricks | 08e3656 | 2013-03-25 15:02:29 -0700 | [diff] [blame] | 136 | void dcache_mmu_enable(void) |
| 137 | { |
| 138 | uint32_t sctlr; |
| 139 | |
| 140 | sctlr = read_sctlr(); |
David Hendricks | 08e3656 | 2013-03-25 15:02:29 -0700 | [diff] [blame] | 141 | sctlr |= SCTLR_C | SCTLR_M; |
| 142 | write_sctlr(sctlr); |
| 143 | } |
| 144 | |
Julius Werner | fd9defc | 2014-01-21 20:11:22 -0800 | [diff] [blame] | 145 | void cache_sync_instructions(void) |
David Hendricks | 08e3656 | 2013-03-25 15:02:29 -0700 | [diff] [blame] | 146 | { |
David Hendricks | f7da3d2 | 2015-01-27 09:27:54 -0800 | [diff] [blame] | 147 | uint32_t sctlr; |
| 148 | |
| 149 | sctlr = read_sctlr(); |
| 150 | |
| 151 | if (sctlr & SCTLR_C) |
| 152 | dcache_clean_all(); |
| 153 | else if (sctlr & SCTLR_I) |
| 154 | dcache_clean_invalidate_all(); |
| 155 | |
Julius Werner | fd9defc | 2014-01-21 20:11:22 -0800 | [diff] [blame] | 156 | iciallu(); /* includes BPIALLU (architecturally) */ |
| 157 | dsb(); |
| 158 | isb(); |
David Hendricks | 2fba5e2 | 2013-03-14 19:06:11 -0700 | [diff] [blame] | 159 | } |