| efdesign98 | 95b6611 | 2011-07-20 13:23:04 -0600 | [diff] [blame^] | 1 | # |
| 2 | # This file is part of the coreboot project. |
| 3 | # |
| 4 | # Copyright (C) 2011 Advanced Micro Devices, Inc. |
| 5 | # |
| 6 | # This program is free software; you can redistribute it and/or modify |
| 7 | # it under the terms of the GNU General Public License as published by |
| 8 | # the Free Software Foundation; version 2 of the License. |
| 9 | # |
| 10 | # This program is distributed in the hope that it will be useful, |
| 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | # GNU General Public License for more details. |
| 14 | # |
| 15 | # You should have received a copy of the GNU General Public License |
| 16 | # along with this program; if not, write to the Free Software |
| 17 | # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | # |
| 19 | |
| 20 | if BOARD_SUPERMICRO_H8QGI |
| 21 | |
| 22 | config BOARD_SPECIFIC_OPTIONS |
| 23 | def_bool y |
| 24 | select ARCH_X86 |
| 25 | select CPU_AMD_AGESA_FAMILY10 |
| 26 | select NORTHBRIDGE_AMD_AGESA_FAMILY10_ROOT_COMPLEX |
| 27 | select NORTHBRIDGE_AMD_AGESA_FAMILY10 |
| 28 | select SOUTHBRIDGE_AMD_SR5650 |
| 29 | select SOUTHBRIDGE_AMD_SP5100 |
| 30 | select SUPERIO_WINBOND_W83627DHG |
| 31 | select BOARD_HAS_FADT |
| 32 | select HAVE_BUS_CONFIG |
| 33 | select HAVE_OPTION_TABLE |
| 34 | select HAVE_PIRQ_TABLE |
| 35 | select HAVE_MP_TABLE |
| 36 | select HAVE_HARD_RESET |
| 37 | select SERIAL_CPU_INIT |
| 38 | select AMDMCT |
| 39 | select HAVE_ACPI_TABLES |
| 40 | select BOARD_ROMSIZE_KB_2048 |
| 41 | select TINY_BOOTBLOCK |
| 42 | #select MMCONF_SUPPORT_DEFAULT #TODO enable it to resolve Multicore IO conflict |
| 43 | |
| 44 | config AMD_AGESA |
| 45 | bool |
| 46 | default y |
| 47 | |
| 48 | config MAINBOARD_DIR |
| 49 | string |
| 50 | default supermicro/h8qgi |
| 51 | |
| 52 | config MAINBOARD_PART_NUMBER |
| 53 | string |
| 54 | default "H8QGI" |
| 55 | |
| 56 | config HW_MEM_HOLE_SIZEK |
| 57 | hex |
| 58 | default 0x200000 |
| 59 | |
| 60 | config MAX_CPUS |
| 61 | int |
| 62 | default 64 |
| 63 | |
| 64 | config MAX_PHYSICAL_CPUS |
| 65 | int |
| 66 | default 16 |
| 67 | |
| 68 | config HW_MEM_HOLE_SIZE_AUTO_INC |
| 69 | bool |
| 70 | default n |
| 71 | |
| 72 | config MEM_TRAIN_SEQ |
| 73 | int |
| 74 | default 2 |
| 75 | |
| 76 | config IRQ_SLOT_COUNT |
| 77 | int |
| 78 | default 11 |
| 79 | |
| 80 | config RAMTOP |
| 81 | hex |
| 82 | default 0x1000000 |
| 83 | |
| 84 | config HEAP_SIZE |
| 85 | hex |
| 86 | default 0xc0000 |
| 87 | |
| 88 | config STACK_SIZE |
| 89 | hex |
| 90 | default 0x10000 |
| 91 | |
| 92 | config ACPI_SSDTX_NUM |
| 93 | int |
| 94 | default 0 |
| 95 | |
| 96 | config RAMBASE |
| 97 | hex |
| 98 | default 0x200000 |
| 99 | |
| 100 | config SIO_PORT |
| 101 | hex |
| 102 | default 0x164E |
| 103 | help |
| 104 | though UARTs are on the NUVOTON BMC, port 0x164E |
| 105 | PS2 keyboard and mouse are on SUPERIO_WINBOND_W83627DHG, port 0x2E |
| 106 | |
| 107 | config DRIVERS_PS2_KEYBOARD |
| 108 | bool |
| 109 | default y |
| 110 | |
| 111 | config WARNINGS_ARE_ERRORS |
| 112 | bool |
| 113 | default n |
| 114 | |
| 115 | config ONBOARD_VGA_IS_PRIMARY |
| 116 | bool |
| 117 | default y |
| 118 | |
| 119 | config VGA_BIOS |
| 120 | bool |
| 121 | default n |
| 122 | |
| 123 | config VGA_BIOS_ID |
| 124 | string |
| 125 | depends on VGA_BIOS |
| 126 | default "102b,0532" |
| 127 | |
| 128 | endif # BOARD_SUPERMICRO_H8QGI |
| 129 | |