blob: bfe00fe4e892a23318795da23e75cc11542f1981 [file] [log] [blame]
Stefan Reinauer9fe20cb2012-12-07 17:18:43 -08001# Warning: This file is included whether or not the if is here.
2# The if controls how the evaluation occurs.
3# (See also src/Kconfig)
Stefan Reinauer9fe20cb2012-12-07 17:18:43 -08004
Stefan Reinauera48ca842015-04-04 01:58:28 +02005source "src/cpu/*/Kconfig"
Patrick Georgi0588d192009-08-12 15:00:51 +00006
Furquan Shaikhfd337812014-04-22 15:16:54 -07007if ARCH_X86
Stefan Reinauer704b5962010-08-30 17:53:13 +00009config CACHE_AS_RAM
Patrick Georgi39ec29c2009-08-27 12:10:50 +000010 bool
Stefan Reinauer314e5512010-04-09 20:36:29 +000011 default !ROMCC
Patrick Georgi39ec29c2009-08-27 12:10:50 +000012
Patrick Georgi0588d192009-08-12 15:00:51 +000013config DCACHE_RAM_BASE
14 hex
Patrick Georgi0588d192009-08-12 15:00:51 +000015
17 hex
Patrick Georgi0588d192009-08-12 15:00:51 +000018
Timothy Pearsonb5e46552015-06-02 13:47:36 -050019config DCACHE_BSP_STACK_SIZE
20 hex
Timothy Pearsonfb39f822015-06-02 20:25:03 -050022config DCACHE_BSP_STACK_SLUSH
23 hex
Timothy Pearsonb5e46552015-06-02 13:47:36 -050025config DCACHE_AP_STACK_SIZE
26 hex
Patrick Georgi0588d192009-08-12 15:00:51 +000028config SMP
29 bool
Myles Watson45bb25f2009-09-22 18:49:08 +000030 default y if MAX_CPUS != 1
Patrick Georgi892b0912009-09-24 09:03:06 +000031 default n
Uwe Hermanna29ad5c2009-10-18 18:35:50 +000032 help
33 This option is used to enable certain functions to make coreboot
34 work correctly on symmetric multi processor (SMP) systems.
Ronald G. Minnich149d6752009-10-01 23:22:50 +000035
Kyösti Mälkki7dfe32c2012-02-14 10:39:17 +020036config AP_SIPI_VECTOR
37 hex
38 default 0xfffff000
39 help
40 This must equal address of ap_sipi_vector from bootblock build.
Patrick Georgi819c7d42012-03-31 13:08:12 +020041
Ronald G. Minnich149d6752009-10-01 23:22:50 +000042config MMX
43 bool
Stefan Reinauera7acc512010-02-25 13:40:49 +000044 help
45 Select MMX in your socket or model Kconfig if your CPU has MMX
46 streaming SIMD instructions. ROMCC can build more efficient
47 code if it can spill to MMX registers.
Ronald G. Minnich149d6752009-10-01 23:22:50 +000048
49config SSE
50 bool
Stefan Reinauera7acc512010-02-25 13:40:49 +000051 help
52 Select SSE in your socket or model Kconfig if your CPU has SSE
53 streaming SIMD instructions. ROMCC can build more efficient
54 code if it can spill to SSE (aka XMM) registers.
56config SSE2
57 bool
Myles Watson34261952010-03-19 02:33:40 +000058 default n
Stefan Reinauera7acc512010-02-25 13:40:49 +000059 help
60 Select SSE2 in your socket or model Kconfig if your CPU has SSE2
61 streaming SIMD instructions. Some parts of coreboot can be built
62 with more efficient code if SSE2 instructions are available.
Patrick Georgi0e9a9252009-10-06 20:48:07 +000063
Stefan Reinauer8aedcbc2010-12-16 23:37:17 +000064endif # ARCH_X86
Alexandru Gagniuc00b579a2012-07-20 00:11:21 -050065
Alexandru Gagniuc66e0c4c2013-12-04 22:21:15 -060066config SUPPORT_CPU_UCODE_IN_CBFS
Alexandru Gagniuc00b579a2012-07-20 00:11:21 -050067 bool
68 default n
Alexandru Gagniuca4061192013-12-04 21:57:15 -060070# This variable is used to determine if we add CPU microcode to CBFS during the
71# build. Microcode can be added manually afterwards, or removed. As a result,
72# code should not rely on this to tell if a microcode update is present or not,
73# and should instead search CBFS.
74# This variable is useful in determining if certain automated post-processing
75# steps can be performed right after the build, such as automatically adding
76# a firmware interface table.
78 bool
Alexandru Gagniuc00b579a2012-07-20 00:11:21 -050081choice
Stefan Reinauer9c29cfa2013-02-27 20:24:11 +010082 prompt "Include CPU microcode in CBFS" if ARCH_X86
Paul Menzelbdaeea52015-03-07 09:15:02 +010083 default CPU_MICROCODE_CBFS_GENERATE if SUPPORT_CPU_UCODE_IN_CBFS && USE_BLOBS
Alexandru Gagniuc66e0c4c2013-12-04 22:21:15 -060084 default CPU_MICROCODE_CBFS_NONE if !SUPPORT_CPU_UCODE_IN_CBFS
Alexandru Gagniuc00b579a2012-07-20 00:11:21 -050085
87 bool "Generate from tree"
88 help
89 Select this option if you want microcode updates to be assembled when
90 building coreboot and included in the final image as a separate CBFS
91 file. Microcode will not be hard-coded into ramstage.
Stefan Tauner0ce2b432013-04-01 13:45:44 +020093 The microcode file may be removed from the ROM image at a later
Alexandru Gagniuc00b579a2012-07-20 00:11:21 -050094 time with cbfstool, if desired.
96 If unsure, select this option.
99 bool "Include external microcode file"
100 help
101 Select this option if you want to include an external file containing
102 the CPU microcode. This will be included as a separate file in CBFS.
103 A word of caution: only select this option if you are sure the
104 microcode that you have is newer than the microcode shipping with
105 coreboot.
Stefan Tauner0ce2b432013-04-01 13:45:44 +0200107 The microcode file may be removed from the ROM image at a later
Alexandru Gagniuc00b579a2012-07-20 00:11:21 -0500108 time with cbfstool, if desired.
110 If unsure, select "Generate from tree"
Alexandru Gagniuc00b579a2012-07-20 00:11:21 -0500112config CPU_MICROCODE_CBFS_NONE
113 bool "Do not include microcode updates"
114 help
115 Select this option if you do not want CPU microcode included in CBFS.
116 Note that for some CPUs, the microcode is hard-coded into the source
117 tree and is not loaded from CBFS. In this case, microcode will still
118 be updated. There is a push to move all microcode to CBFS, but this
119 change is not implemented for all CPUs.
121 This option currently applies to:
122 - Intel SandyBridge/IvyBridge
123 - VIA Nano
125 Microcode may be added to the ROM image at a later time with cbfstool,
126 if desired.
128 If unsure, select "Generate from tree"
130 The GOOD:
131 Microcode updates intend to solve issues that have been discovered
132 after CPU production. The expected effect is that systems work as
133 intended with the updated microcode, but we have also seen cases where
134 issues were solved by not applying microcode updates.
136 The BAD:
137 Note that some operating system include these same microcode patches,
138 so you may need to also disable microcode updates in your operating
139 system for this option to have an effect.
141 The UGLY:
142 A word of CAUTION: some CPUs depend on microcode updates to function
143 correctly. Not updating the microcode may leave the CPU operating at
144 less than optimal performance, or may cause outright hangups.
145 There are CPUs where coreboot cannot properly initialize the CPU
146 without microcode updates
147 For example, if running with the factory microcode, some Intel
148 SandyBridge CPUs may hang when enabling CAR, or some VIA Nano CPUs
149 will hang when changing the frequency.
151 Make sure you have a way of flashing the ROM externally before
152 selecting this option.
Jens Rottmann686dc0d2013-02-18 17:26:01 +0100155
157 string "Path and filename of CPU microcode"
159 default "cpu_microcode.bin"
160 help
161 The path and filename of the file containing the CPU microcode.