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review.coreboot.org / coreboot / 9533d836d77cf126ef3954eaf8f1e3acd0a1356a / . / src / mainboard / asrock / imb-a180 / irq_tables.c
blob: 845400724a2ef1c69d058b0431036a1b83ea22d5 [file] [log] [blame]
WANG Siyuanf77f7342013-08-13 17:09:51 +0800[diff] [blame]1/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2012 Advanced Micro Devices, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18 */
19
20#include <console/console.h>
21#include <device/pci.h>
22#include <string.h>
23#include <stdint.h>
24#include <arch/pirq_routing.h>
25#include <cpu/amd/amdfam16.h>
26
27static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
28 u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
29 u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,
30 u8 slot, u8 rfu)
31{
32 pirq_info->bus = bus;
33 pirq_info->devfn = devfn;
34 pirq_info->irq[0].link = link0;
35 pirq_info->irq[0].bitmap = bitmap0;
36 pirq_info->irq[1].link = link1;
37 pirq_info->irq[1].bitmap = bitmap1;
38 pirq_info->irq[2].link = link2;
39 pirq_info->irq[2].bitmap = bitmap2;
40 pirq_info->irq[3].link = link3;
41 pirq_info->irq[3].bitmap = bitmap3;
42 pirq_info->slot = slot;
43 pirq_info->rfu = rfu;
44}
45
46extern u8 bus_isa;
Kyösti Mälkki4f9bf7e2013-09-09 09:23:19 +0300[diff] [blame]47extern u8 bus_yangtze[6];
WANG Siyuanf77f7342013-08-13 17:09:51 +0800[diff] [blame]48extern unsigned long sbdn_yangtze;
49
50unsigned long write_pirq_routing_table(unsigned long addr)
51{
52 struct irq_routing_table *pirq;
53 struct irq_info *pirq_info;
54 u32 slot_num;
55 u8 *v;
56
57 u8 sum = 0;
58 int i;
59
60 get_bus_conf(); /* it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c */
61
62 /* Align the table to be 16 byte aligned. */
63 addr += 15;
64 addr &= ~15;
65
Kyösti Mälkki9533d832014-06-26 05:30:54 +0300[diff] [blame^]66 /* This table must be between 0xf0000 & 0x100000 */
WANG Siyuanf77f7342013-08-13 17:09:51 +0800[diff] [blame]67 printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
68
69 pirq = (void *)(addr);
70 v = (u8 *) (addr);
71
72 pirq->signature = PIRQ_SIGNATURE;
73 pirq->version = PIRQ_VERSION;
74
75 pirq->rtr_bus = bus_yangtze[0];
76 pirq->rtr_devfn = ((sbdn_yangtze + 0x14) << 3) | 4;
77
78 pirq->exclusive_irqs = 0;
79
80 pirq->rtr_vendor = 0x1002;
81 pirq->rtr_device = 0x4384;
82
83 pirq->miniport_data = 0;
84
85 memset(pirq->rfu, 0, sizeof(pirq->rfu));
86
87 pirq_info = (void *)(&pirq->checksum + 1);
88 slot_num = 0;
89
90 /* pci bridge */
91 write_pirq_info(pirq_info, bus_yangtze[0], ((sbdn_yangtze + 0x14) << 3) | 4,
92 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0,
93 0);
94 pirq_info++;
95
96 slot_num++;
97
98 pirq->size = 32 + 16 * slot_num;
99
100 for (i = 0; i < pirq->size; i++)
101 sum += v[i];
102
103 sum = pirq->checksum - sum;
104
105 if (sum != pirq->checksum) {
106 pirq->checksum = sum;
107 }
108
109 printk(BIOS_INFO, "write_pirq_routing_table done.\n");
110
111 return (unsigned long)pirq_info;
112}