blob: e6ce49dcca9f1192d3ad90996f03859dab2b531f [file] [log] [blame]
Ronald G. Minnichf89e6b22012-12-10 16:13:43 -08001##
2## This file is part of the coreboot project.
3##
Stefan Reinauer08dc3572013-05-14 16:57:50 -07004## Copyright 2012 Google Inc.
Ronald G. Minnichf89e6b22012-12-10 16:13:43 -08005##
6## This program is free software; you can redistribute it and/or modify
7## it under the terms of the GNU General Public License as published by
8## the Free Software Foundation; version 2 of the License.
9##
10## This program is distributed in the hope that it will be useful,
11## but WITHOUT ANY WARRANTY; without even the implied warranty of
12## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13## GNU General Public License for more details.
14##
15## You should have received a copy of the GNU General Public License
16## along with this program; if not, write to the Free Software
17## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18##
19
Ronald G. Minnichf89e6b22012-12-10 16:13:43 -080020chip cpu/samsung/exynos5250
Ronald G. Minnich767edfc2013-04-09 14:32:32 -070021 device cpu_cluster 0 on end
22 register "xres" = "1366"
23 register "yres" = "768"
Ronald G. Minnich9518b562013-09-19 16:45:22 -070024 register "framebuffer_bits_per_pixel" = "16"
Ronald G. Minnich767edfc2013-04-09 14:32:32 -070025 # complex magic timing!
26 register "clkval_f" = "2"
27 register "upper_margin" = "14"
28 register "lower_margin" = "3"
29 register "vsync" = "5"
30 register "left_margin" = "80"
31 register "right_margin" = "48"
32 register "hsync" = "32"
David Hendricks249cdc32013-02-15 16:23:23 -080033end