Ronald G. Minnich | 45df596 | 2013-07-08 14:02:57 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright 2013 Google Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | */ |
| 19 | |
| 20 | #include <types.h> |
| 21 | #include <string.h> |
| 22 | #include <stdlib.h> |
| 23 | #include <device/device.h> |
| 24 | #include <device/device.h> |
| 25 | #include <device/pci_def.h> |
| 26 | #include <device/pci_ops.h> |
| 27 | #include <console/console.h> |
| 28 | #include <delay.h> |
| 29 | #include <pc80/mc146818rtc.h> |
| 30 | #include <arch/acpi.h> |
| 31 | #include <arch/io.h> |
| 32 | #include <arch/interrupt.h> |
| 33 | #include <boot/coreboot_tables.h> |
| 34 | #include "hda_verb.h" |
| 35 | #include <smbios.h> |
| 36 | #include <device/pci.h> |
| 37 | #include <ec/google/chromeec/ec.h> |
| 38 | #include <cbfs_core.h> |
| 39 | |
| 40 | #include <cpu/x86/tsc.h> |
| 41 | #include <cpu/x86/cache.h> |
| 42 | #include <cpu/x86/mtrr.h> |
| 43 | #include <cpu/x86/msr.h> |
| 44 | #include <edid.h> |
| 45 | #include <drivers/intel/gma/i915.h> |
Furquan Shaikh | c1c6dcf | 2013-08-06 13:48:12 -0700 | [diff] [blame] | 46 | #include "mainboard.h" |
Furquan Shaikh | cb61ea7 | 2013-08-15 15:23:58 -0700 | [diff] [blame] | 47 | |
Ronald G. Minnich | 45df596 | 2013-07-08 14:02:57 -0700 | [diff] [blame] | 48 | /* |
| 49 | * Here is the rough outline of how we bring up the display: |
| 50 | * 1. Upon power-on Sink generates a hot plug detection pulse thru HPD |
| 51 | * 2. Source determines video mode by reading DPCD receiver capability field |
| 52 | * (DPCD 00000h to 0000Dh) including eDP CP capability register (DPCD |
| 53 | * 0000Dh). |
| 54 | * 3. Sink replies DPCD receiver capability field. |
| 55 | * 4. Source starts EDID read thru I2C-over-AUX. |
| 56 | * 5. Sink replies EDID thru I2C-over-AUX. |
| 57 | * 6. Source determines link configuration, such as MAX_LINK_RATE and |
| 58 | * MAX_LANE_COUNT. Source also determines which type of eDP Authentication |
| 59 | * method to use and writes DPCD link configuration field (DPCD 00100h to |
| 60 | * 0010Ah) including eDP configuration set (DPCD 0010Ah). |
| 61 | * 7. Source starts link training. Sink does clock recovery and equalization. |
| 62 | * 8. Source reads DPCD link status field (DPCD 00200h to 0020Bh). |
| 63 | * 9. Sink replies DPCD link status field. If main link is not stable, Source |
| 64 | * repeats Step 7. |
| 65 | * 10. Source sends MSA (Main Stream Attribute) data. Sink extracts video |
| 66 | * parameters and recovers stream clock. |
| 67 | * 11. Source sends video data. |
| 68 | */ |
| 69 | |
| 70 | /* how many bytes do we need for the framebuffer? |
| 71 | * Well, this gets messy. To get an exact answer, we have |
| 72 | * to ask the panel, but we'd rather zero the memory |
| 73 | * and set up the gtt while the panel powers up. So, |
| 74 | * we take a reasonable guess, secure in the knowledge that the |
| 75 | * MRC has to overestimate the number of bytes used. |
| 76 | * 8 MiB is a very safe guess. There may be a better way later, but |
| 77 | * fact is, the initial framebuffer is only very temporary. And taking |
| 78 | * a little long is ok; this is done much faster than the AUX |
| 79 | * channel is ready for IO. |
| 80 | */ |
| 81 | #define FRAME_BUFFER_BYTES (8*MiB) |
| 82 | /* how many 4096-byte pages do we need for the framebuffer? |
| 83 | * There are hard ways to get this, and easy ways: |
| 84 | * there are FRAME_BUFFER_BYTES/4096 pages, since pages are 4096 |
| 85 | * on this chip (and in fact every Intel graphics chip we've seen). |
| 86 | */ |
| 87 | #define FRAME_BUFFER_PAGES (FRAME_BUFFER_BYTES/(4096)) |
| 88 | |
| 89 | static unsigned int *mmio; |
| 90 | static unsigned int graphics; |
Ronald G. Minnich | 45df596 | 2013-07-08 14:02:57 -0700 | [diff] [blame] | 91 | static unsigned int physbase; |
Ronald G. Minnich | 45df596 | 2013-07-08 14:02:57 -0700 | [diff] [blame] | 92 | |
Ronald G. Minnich | 45df596 | 2013-07-08 14:02:57 -0700 | [diff] [blame] | 93 | void ug1(int); |
| 94 | void ug2(int); |
| 95 | void ug22(int); |
| 96 | void ug3(int); |
| 97 | |
Ronald G. Minnich | 45df596 | 2013-07-08 14:02:57 -0700 | [diff] [blame] | 98 | /* GTT is the Global Translation Table for the graphics pipeline. |
| 99 | * It is used to translate graphics addresses to physical |
| 100 | * memory addresses. As in the CPU, GTTs map 4K pages. |
| 101 | * The setgtt function adds a further bit of flexibility: |
| 102 | * it allows you to set a range (the first two parameters) to point |
| 103 | * to a physical address (third parameter);the physical address is |
| 104 | * incremented by a count (fourth parameter) for each GTT in the |
| 105 | * range. |
| 106 | * Why do it this way? For ultrafast startup, |
| 107 | * we can point all the GTT entries to point to one page, |
| 108 | * and set that page to 0s: |
| 109 | * memset(physbase, 0, 4096); |
| 110 | * setgtt(0, 4250, physbase, 0); |
| 111 | * this takes about 2 ms, and is a win because zeroing |
| 112 | * the page takes a up to 200 ms. |
| 113 | * This call sets the GTT to point to a linear range of pages |
| 114 | * starting at physbase. |
| 115 | */ |
| 116 | |
Furquan Shaikh | 77f48cd | 2013-08-19 10:16:50 -0700 | [diff] [blame] | 117 | #define GTT_PTE_BASE (2 << 20) |
| 118 | |
Ronald G. Minnich | 45df596 | 2013-07-08 14:02:57 -0700 | [diff] [blame] | 119 | static void |
| 120 | setgtt(int start, int end, unsigned long base, int inc) |
| 121 | { |
| 122 | int i; |
| 123 | |
| 124 | for(i = start; i < end; i++){ |
| 125 | u32 word = base + i*inc; |
| 126 | /* note: we've confirmed by checking |
| 127 | * the values that mrc does no |
| 128 | * useful setup before we run this. |
| 129 | */ |
Furquan Shaikh | 77f48cd | 2013-08-19 10:16:50 -0700 | [diff] [blame] | 130 | gtt_write(GTT_PTE_BASE + i * 4, word|1); |
| 131 | gtt_read(GTT_PTE_BASE + i * 4); |
Ronald G. Minnich | 45df596 | 2013-07-08 14:02:57 -0700 | [diff] [blame] | 132 | } |
| 133 | } |
| 134 | |
| 135 | static int i915_init_done = 0; |
| 136 | |
| 137 | /* fill the palette. */ |
| 138 | static void palette(void) |
| 139 | { |
| 140 | int i; |
| 141 | unsigned long color = 0; |
| 142 | |
| 143 | for(i = 0; i < 256; i++, color += 0x010101){ |
Furquan Shaikh | 77f48cd | 2013-08-19 10:16:50 -0700 | [diff] [blame] | 144 | gtt_write(_LGC_PALETTE_A + (i<<2),color); |
Ronald G. Minnich | 45df596 | 2013-07-08 14:02:57 -0700 | [diff] [blame] | 145 | } |
| 146 | } |
| 147 | |
Ronald G. Minnich | 45df596 | 2013-07-08 14:02:57 -0700 | [diff] [blame] | 148 | void dp_init_dim_regs(struct intel_dp *dp); |
| 149 | void dp_init_dim_regs(struct intel_dp *dp) |
| 150 | { |
| 151 | struct edid *edid = &(dp->edid); |
| 152 | |
Ronald G. Minnich | 9518b56 | 2013-09-19 16:45:22 -0700 | [diff] [blame^] | 153 | dp->bytes_per_pixel = edid->framebuffer_bits_per_pixel / 8; |
Ronald G. Minnich | 45df596 | 2013-07-08 14:02:57 -0700 | [diff] [blame] | 154 | |
| 155 | dp->stride = edid->bytes_per_line; |
| 156 | |
| 157 | dp->htotal = (edid->ha - 1) | ((edid->ha + edid->hbl - 1) << 16); |
| 158 | |
| 159 | dp->hblank = (edid->ha - 1) | ((edid->ha + edid->hbl - 1) << 16); |
| 160 | |
| 161 | dp->hsync = (edid->ha + edid->hso - 1) | |
| 162 | ((edid->ha + edid->hso + edid->hspw - 1) << 16); |
| 163 | |
| 164 | dp->vtotal = (edid->va - 1) | ((edid->va + edid->vbl - 1) << 16); |
| 165 | |
| 166 | dp->vblank = (edid->va - 1) | ((edid->va + edid->vbl - 1) << 16); |
| 167 | |
| 168 | dp->vsync = (edid->va + edid->vso - 1) | |
| 169 | ((edid->va + edid->vso + edid->vspw - 1) << 16); |
| 170 | |
| 171 | /* PIPEASRC is wid-1 x ht-1 */ |
| 172 | dp->pipesrc = (edid->ha-1)<<16 | (edid->va-1); |
| 173 | |
| 174 | dp->pfa_pos = 0; |
| 175 | |
| 176 | dp->pfa_ctl = 0x80800000; |
| 177 | |
| 178 | dp->pfa_sz = (edid->ha << 16) | (edid->va); |
| 179 | |
Furquan Shaikh | d0a81f7 | 2013-07-30 12:41:08 -0700 | [diff] [blame] | 180 | dp->flags = intel_ddi_calc_transcoder_flags(3 * 6, /* bits per color is 6 */ |
| 181 | dp->port, |
| 182 | dp->pipe, |
| 183 | dp->type, |
| 184 | dp->lane_count, |
Furquan Shaikh | 771c3ac | 2013-08-01 13:58:17 -0700 | [diff] [blame] | 185 | dp->pfa_sz, |
| 186 | dp->edid.phsync == '+'?1:0, |
| 187 | dp->edid.pvsync == '+'?1:0); |
Furquan Shaikh | d0a81f7 | 2013-07-30 12:41:08 -0700 | [diff] [blame] | 188 | |
Furquan Shaikh | db3157c | 2013-07-31 16:47:31 -0700 | [diff] [blame] | 189 | dp->transcoder = intel_ddi_get_transcoder(dp->port, |
| 190 | dp->pipe); |
| 191 | |
Ronald G. Minnich | 9518b56 | 2013-09-19 16:45:22 -0700 | [diff] [blame^] | 192 | intel_dp_compute_m_n(dp->pipe_bits_per_pixel, |
Furquan Shaikh | 6b19071 | 2013-07-22 16:18:31 -0700 | [diff] [blame] | 193 | dp->lane_count, |
| 194 | dp->edid.pixel_clock, |
| 195 | dp->edid.link_clock, |
| 196 | &dp->m_n); |
| 197 | |
Ronald G. Minnich | 45df596 | 2013-07-08 14:02:57 -0700 | [diff] [blame] | 198 | printk(BIOS_SPEW, "dp->stride = 0x%08x\n",dp->stride); |
| 199 | printk(BIOS_SPEW, "dp->htotal = 0x%08x\n", dp->htotal); |
| 200 | printk(BIOS_SPEW, "dp->hblank = 0x%08x\n", dp->hblank); |
| 201 | printk(BIOS_SPEW, "dp->hsync = 0x%08x\n", dp->hsync); |
| 202 | printk(BIOS_SPEW, "dp->vtotal = 0x%08x\n", dp->vtotal); |
| 203 | printk(BIOS_SPEW, "dp->vblank = 0x%08x\n", dp->vblank); |
| 204 | printk(BIOS_SPEW, "dp->vsync = 0x%08x\n", dp->vsync); |
| 205 | printk(BIOS_SPEW, "dp->pipesrc = 0x%08x\n", dp->pipesrc); |
| 206 | printk(BIOS_SPEW, "dp->pfa_pos = 0x%08x\n", dp->pfa_pos); |
| 207 | printk(BIOS_SPEW, "dp->pfa_ctl = 0x%08x\n", dp->pfa_ctl); |
| 208 | printk(BIOS_SPEW, "dp->pfa_sz = 0x%08x\n", dp->pfa_sz); |
Furquan Shaikh | 6b19071 | 2013-07-22 16:18:31 -0700 | [diff] [blame] | 209 | printk(BIOS_SPEW, "dp->link_m = 0x%08x\n", dp->m_n.link_m); |
| 210 | printk(BIOS_SPEW, "dp->link_n = 0x%08x\n", dp->m_n.link_n); |
| 211 | printk(BIOS_SPEW, "0x6f030 = 0x%08x\n", TU_SIZE(dp->m_n.tu) | dp->m_n.gmch_m); |
| 212 | printk(BIOS_SPEW, "0x6f030 = 0x%08x\n", dp->m_n.gmch_m); |
| 213 | printk(BIOS_SPEW, "0x6f034 = 0x%08x\n", dp->m_n.gmch_n); |
Furquan Shaikh | d0a81f7 | 2013-07-30 12:41:08 -0700 | [diff] [blame] | 214 | printk(BIOS_SPEW, "dp->flags = 0x%08x\n", dp->flags); |
Furquan Shaikh | 6b19071 | 2013-07-22 16:18:31 -0700 | [diff] [blame] | 215 | } |
| 216 | |
| 217 | int intel_dp_bw_code_to_link_rate(u8 link_bw); |
| 218 | |
| 219 | int intel_dp_bw_code_to_link_rate(u8 link_bw) |
| 220 | { |
| 221 | switch (link_bw) { |
| 222 | case DP_LINK_BW_1_62: |
| 223 | default: |
| 224 | return 162000; |
| 225 | case DP_LINK_BW_2_7: |
| 226 | return 270000; |
| 227 | case DP_LINK_BW_5_4: |
| 228 | return 540000; |
| 229 | } |
Ronald G. Minnich | 45df596 | 2013-07-08 14:02:57 -0700 | [diff] [blame] | 230 | } |
| 231 | |
Furquan Shaikh | 997be3d | 2013-07-31 13:17:30 -0700 | [diff] [blame] | 232 | void mainboard_train_link(struct intel_dp *intel_dp) |
| 233 | { |
| 234 | u8 read_val; |
| 235 | u8 link_status[DP_LINK_STATUS_SIZE]; |
| 236 | |
Furquan Shaikh | 77f48cd | 2013-08-19 10:16:50 -0700 | [diff] [blame] | 237 | gtt_write(DP_TP_CTL(intel_dp->port),DP_TP_CTL_ENABLE | DP_TP_CTL_ENHANCED_FRAME_ENABLE); |
| 238 | gtt_write(DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_SYNC_VS_HIGH |0x80000011); |
Furquan Shaikh | 997be3d | 2013-07-31 13:17:30 -0700 | [diff] [blame] | 239 | |
| 240 | intel_dp_get_training_pattern(intel_dp, &read_val); |
| 241 | intel_dp_set_training_pattern(intel_dp, DP_TRAINING_PATTERN_1 | DP_LINK_QUAL_PATTERN_DISABLE | DP_SYMBOL_ERROR_COUNT_BOTH); |
| 242 | intel_dp_get_lane_count(intel_dp, &read_val); |
| 243 | intel_dp_set_training_lane0(intel_dp, DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0); |
| 244 | intel_dp_get_link_status(intel_dp, link_status); |
| 245 | |
Furquan Shaikh | 77f48cd | 2013-08-19 10:16:50 -0700 | [diff] [blame] | 246 | gtt_write(DP_TP_CTL(intel_dp->port),DP_TP_CTL_ENABLE | DP_TP_CTL_ENHANCED_FRAME_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT2); |
Furquan Shaikh | 997be3d | 2013-07-31 13:17:30 -0700 | [diff] [blame] | 247 | |
| 248 | intel_dp_get_training_pattern(intel_dp, &read_val); |
| 249 | intel_dp_set_training_pattern(intel_dp, DP_TRAINING_PATTERN_2 | DP_LINK_QUAL_PATTERN_DISABLE | DP_SYMBOL_ERROR_COUNT_BOTH); |
| 250 | intel_dp_get_link_status(intel_dp, link_status); |
| 251 | intel_dp_get_lane_align_status(intel_dp, &read_val); |
| 252 | intel_dp_get_training_pattern(intel_dp, &read_val); |
| 253 | intel_dp_set_training_pattern(intel_dp, DP_TRAINING_PATTERN_DISABLE | DP_LINK_QUAL_PATTERN_DISABLE | DP_SYMBOL_ERROR_COUNT_BOTH); |
| 254 | } |
| 255 | |
Furquan Shaikh | 77f48cd | 2013-08-19 10:16:50 -0700 | [diff] [blame] | 256 | #define TEST_GFX 0 |
| 257 | |
| 258 | #if TEST_GFX |
| 259 | static void test_gfx(struct intel_dp *dp) |
| 260 | { |
| 261 | int i; |
| 262 | |
| 263 | /* This is a sanity test code which fills the screen with two bands -- |
| 264 | green and blue. It is very useful to ensure all the initializations |
| 265 | are made right. Thus, to be used only for testing, not otherwise |
| 266 | */ |
| 267 | for (i = 0; i < (dp->edid.va - 4); i++) { |
| 268 | u32 *l; |
| 269 | int j; |
| 270 | u32 tcolor = 0x0ff; |
| 271 | for (j = 0; j < (dp->edid.ha-4); j++) { |
| 272 | if (j == (dp->edid.ha/2)) { |
| 273 | tcolor = 0xff00; |
| 274 | } |
| 275 | l = (u32*)(graphics + i * dp->stride + j * sizeof(tcolor)); |
| 276 | memcpy(l,&tcolor,sizeof(tcolor)); |
| 277 | } |
| 278 | } |
| 279 | } |
| 280 | #else |
| 281 | static void test_gfx(struct intel_dp *dp) {} |
| 282 | #endif |
| 283 | |
Furquan Shaikh | c1c6dcf | 2013-08-06 13:48:12 -0700 | [diff] [blame] | 284 | |
| 285 | void mainboard_set_port_clk_dp(struct intel_dp *intel_dp) |
| 286 | { |
| 287 | u32 ddi_pll_sel = 0; |
| 288 | |
| 289 | switch (intel_dp->link_bw) { |
| 290 | case DP_LINK_BW_1_62: |
| 291 | ddi_pll_sel = PORT_CLK_SEL_LCPLL_810; |
| 292 | break; |
| 293 | case DP_LINK_BW_2_7: |
| 294 | ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350; |
| 295 | break; |
| 296 | case DP_LINK_BW_5_4: |
| 297 | ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700; |
| 298 | break; |
| 299 | default: |
| 300 | printk(BIOS_ERR, "invalid link bw %d\n", intel_dp->link_bw); |
| 301 | return; |
| 302 | } |
| 303 | |
| 304 | gtt_write(PORT_CLK_SEL(intel_dp->port), ddi_pll_sel); |
| 305 | } |
| 306 | |
Furquan Shaikh | 77f48cd | 2013-08-19 10:16:50 -0700 | [diff] [blame] | 307 | int i915lightup(unsigned int pphysbase, unsigned int pmmio, |
| 308 | unsigned int pgfx, unsigned int init_fb) |
Ronald G. Minnich | 45df596 | 2013-07-08 14:02:57 -0700 | [diff] [blame] | 309 | { |
| 310 | int must_cycle_power = 0; |
| 311 | struct intel_dp adp, *dp = &adp; |
Ronald G. Minnich | 45df596 | 2013-07-08 14:02:57 -0700 | [diff] [blame] | 312 | int i; |
| 313 | int edid_ok; |
Ronald G. Minnich | 45df596 | 2013-07-08 14:02:57 -0700 | [diff] [blame] | 314 | int pixels = FRAME_BUFFER_BYTES/64; |
| 315 | |
| 316 | mmio = (void *)pmmio; |
Ronald G. Minnich | 45df596 | 2013-07-08 14:02:57 -0700 | [diff] [blame] | 317 | physbase = pphysbase; |
| 318 | graphics = pgfx; |
| 319 | printk(BIOS_SPEW, |
| 320 | "i915lightup: graphics %p mmio %p" |
Furquan Shaikh | 77f48cd | 2013-08-19 10:16:50 -0700 | [diff] [blame] | 321 | "physbase %08x\n", |
| 322 | (void *)graphics, mmio, physbase); |
Ronald G. Minnich | 45df596 | 2013-07-08 14:02:57 -0700 | [diff] [blame] | 323 | |
| 324 | void runio(struct intel_dp *dp); |
| 325 | void runlinux(struct intel_dp *dp); |
Furquan Shaikh | 77f48cd | 2013-08-19 10:16:50 -0700 | [diff] [blame] | 326 | dp->gen = 8; // This is gen 8 which we believe is Haswell |
Ronald G. Minnich | 45df596 | 2013-07-08 14:02:57 -0700 | [diff] [blame] | 327 | dp->is_haswell = 1; |
| 328 | dp->DP = 0x2; |
| 329 | /* These values are used for training the link */ |
| 330 | dp->lane_count = 2; |
| 331 | dp->link_bw = DP_LINK_BW_2_7; |
| 332 | dp->panel_power_down_delay = 600; |
| 333 | dp->panel_power_up_delay = 200; |
| 334 | dp->panel_power_cycle_delay = 600; |
Furquan Shaikh | d0a81f7 | 2013-07-30 12:41:08 -0700 | [diff] [blame] | 335 | dp->pipe = PIPE_A; |
| 336 | dp->port = PORT_A; |
Furquan Shaikh | 77f48cd | 2013-08-19 10:16:50 -0700 | [diff] [blame] | 337 | dp->plane = PLANE_A; |
Ronald G. Minnich | 45df596 | 2013-07-08 14:02:57 -0700 | [diff] [blame] | 338 | dp->clock = 160000; |
Ronald G. Minnich | 9518b56 | 2013-09-19 16:45:22 -0700 | [diff] [blame^] | 339 | dp->pipe_bits_per_pixel = 32; |
Ronald G. Minnich | 45df596 | 2013-07-08 14:02:57 -0700 | [diff] [blame] | 340 | dp->type = INTEL_OUTPUT_EDP; |
| 341 | dp->output_reg = DP_A; |
| 342 | /* observed from YABEL. */ |
| 343 | dp->aux_clock_divider = 0xe1; |
| 344 | dp->precharge = 3; |
| 345 | |
Furquan Shaikh | cb61ea7 | 2013-08-15 15:23:58 -0700 | [diff] [blame] | 346 | /* 1. Normal mode: Set the first page to zero and make |
| 347 | all GTT entries point to the same page |
| 348 | 2. Developer/Recovery mode: We do not zero out all |
| 349 | the pages pointed to by GTT in order to avoid wasting time */ |
| 350 | if (init_fb) |
| 351 | setgtt(0, FRAME_BUFFER_PAGES, physbase, 4096); |
| 352 | else { |
| 353 | setgtt(0, FRAME_BUFFER_PAGES, physbase, 0); |
| 354 | memset((void*)graphics, 0, 4096); |
| 355 | } |
| 356 | |
Ronald G. Minnich | 45df596 | 2013-07-08 14:02:57 -0700 | [diff] [blame] | 357 | dp->address = 0x50; |
| 358 | |
| 359 | if ( !intel_dp_get_dpcd(dp) ) |
| 360 | goto fail; |
| 361 | |
| 362 | intel_dp_i2c_aux_ch(dp, MODE_I2C_WRITE, 0, NULL); |
| 363 | for(dp->edidlen = i = 0; i < sizeof(dp->rawedid); i++){ |
| 364 | if (intel_dp_i2c_aux_ch(dp, MODE_I2C_READ, |
| 365 | 0x50, &dp->rawedid[i]) < 0) |
| 366 | break; |
| 367 | dp->edidlen++; |
| 368 | } |
| 369 | |
| 370 | edid_ok = decode_edid(dp->rawedid, dp->edidlen, &dp->edid); |
| 371 | printk(BIOS_SPEW, "decode edid returns %d\n", edid_ok); |
| 372 | |
Furquan Shaikh | 6b19071 | 2013-07-22 16:18:31 -0700 | [diff] [blame] | 373 | dp->edid.link_clock = intel_dp_bw_code_to_link_rate(dp->link_bw); |
| 374 | |
| 375 | printk(BIOS_SPEW, "pixel_clock is %i, link_clock is %i\n",dp->edid.pixel_clock, dp->edid.link_clock); |
| 376 | |
Ronald G. Minnich | 45df596 | 2013-07-08 14:02:57 -0700 | [diff] [blame] | 377 | dp_init_dim_regs(dp); |
| 378 | |
Furquan Shaikh | 77f48cd | 2013-08-19 10:16:50 -0700 | [diff] [blame] | 379 | intel_ddi_set_pipe_settings(dp); |
Ronald G. Minnich | 45df596 | 2013-07-08 14:02:57 -0700 | [diff] [blame] | 380 | |
| 381 | runio(dp); |
Ronald G. Minnich | 45df596 | 2013-07-08 14:02:57 -0700 | [diff] [blame] | 382 | |
Furquan Shaikh | cb61ea7 | 2013-08-15 15:23:58 -0700 | [diff] [blame] | 383 | palette(); |
Ronald G. Minnich | 45df596 | 2013-07-08 14:02:57 -0700 | [diff] [blame] | 384 | |
| 385 | pixels = dp->edid.ha * (dp->edid.va-4) * 4; |
| 386 | printk(BIOS_SPEW, "ha=%d, va=%d\n",dp->edid.ha, dp->edid.va); |
| 387 | |
Furquan Shaikh | 77f48cd | 2013-08-19 10:16:50 -0700 | [diff] [blame] | 388 | test_gfx(dp); |
Ronald G. Minnich | 45df596 | 2013-07-08 14:02:57 -0700 | [diff] [blame] | 389 | |
| 390 | set_vbe_mode_info_valid(&dp->edid, graphics); |
| 391 | i915_init_done = 1; |
Kyösti Mälkki | ab56b3b | 2013-11-28 16:44:51 +0200 | [diff] [blame] | 392 | return i915_init_done; |
Ronald G. Minnich | 45df596 | 2013-07-08 14:02:57 -0700 | [diff] [blame] | 393 | |
| 394 | fail: |
| 395 | printk(BIOS_SPEW, "Graphics could not be started;"); |
| 396 | if (0 && must_cycle_power){ |
| 397 | printk(BIOS_SPEW, "Turn off power and wait ..."); |
Furquan Shaikh | 77f48cd | 2013-08-19 10:16:50 -0700 | [diff] [blame] | 398 | gtt_write(PCH_PP_CONTROL,0xabcd0000); |
Ronald G. Minnich | 45df596 | 2013-07-08 14:02:57 -0700 | [diff] [blame] | 399 | udelay(600000); |
Furquan Shaikh | 77f48cd | 2013-08-19 10:16:50 -0700 | [diff] [blame] | 400 | gtt_write(PCH_PP_CONTROL,0xabcd000f); |
Ronald G. Minnich | 45df596 | 2013-07-08 14:02:57 -0700 | [diff] [blame] | 401 | } |
| 402 | printk(BIOS_SPEW, "Returning.\n"); |
| 403 | return 0; |
| 404 | } |