Ronald G. Minnich | 99451b1 | 2013-06-27 10:42:59 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright 2012 Google Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | */ |
| 19 | |
| 20 | #include <drivers/intel/gma/i915_reg.h> |
| 21 | #include <drivers/intel/gma/drm_dp_helper.h> |
| 22 | #include <edid.h> |
| 23 | |
| 24 | /* port types. We stick with the same defines as the kernel */ |
| 25 | #define INTEL_OUTPUT_UNUSED 0 |
| 26 | #define INTEL_OUTPUT_ANALOG 1 |
| 27 | #define INTEL_OUTPUT_DVO 2 |
| 28 | #define INTEL_OUTPUT_SDVO 3 |
| 29 | #define INTEL_OUTPUT_LVDS 4 |
| 30 | #define INTEL_OUTPUT_TVOUT 5 |
| 31 | #define INTEL_OUTPUT_HDMI 6 |
| 32 | #define INTEL_OUTPUT_DISPLAYPORT 7 |
| 33 | #define INTEL_OUTPUT_EDP 8 |
| 34 | |
| 35 | /* things that are, strangely, not defined anywhere? */ |
| 36 | #define PCH_PP_UNLOCK 0xabcd0000 |
| 37 | #define WMx_LP_SR_EN (1<<31) |
| 38 | #define PRB0_TAIL 0x02030 |
| 39 | #define PRB0_HEAD 0x02034 |
| 40 | #define PRB0_START 0x02038 |
| 41 | #define PRB0_CTL 0x0203c |
| 42 | |
Furquan Shaikh | d0a81f7 | 2013-07-30 12:41:08 -0700 | [diff] [blame] | 43 | enum port { |
| 44 | PORT_A = 0, |
| 45 | PORT_B, |
| 46 | PORT_C, |
| 47 | PORT_D, |
| 48 | PORT_E, |
| 49 | I915_NUM_PORTS |
| 50 | }; |
| 51 | |
| 52 | enum pipe { |
| 53 | PIPE_A = 0, |
| 54 | PIPE_B, |
| 55 | PIPE_C, |
| 56 | I915_NUM_PIPES |
| 57 | }; |
| 58 | |
Furquan Shaikh | db3157c | 2013-07-31 16:47:31 -0700 | [diff] [blame] | 59 | enum transcoder { |
| 60 | TRANSCODER_A = 0, |
| 61 | TRANSCODER_B, |
| 62 | TRANSCODER_C, |
| 63 | TRANSCODER_EDP = 0xF, |
| 64 | }; |
| 65 | |
Furquan Shaikh | 77f48cd | 2013-08-19 10:16:50 -0700 | [diff] [blame] | 66 | enum plane { |
| 67 | PLANE_A = 0, |
| 68 | PLANE_B, |
| 69 | PLANE_C, |
| 70 | }; |
| 71 | |
Ronald G. Minnich | 99451b1 | 2013-06-27 10:42:59 -0700 | [diff] [blame] | 72 | /* debug enums. These are for printks that, due to their place in the |
| 73 | * middle of graphics device IO, might change timing. Use with care |
| 74 | * or not at all. |
| 75 | */ |
| 76 | enum { |
| 77 | vio = 2, /* dump every IO */ |
| 78 | vspin = 4, /* print # of times we spun on a register value */ |
| 79 | }; |
| 80 | |
| 81 | /* The mainboard must provide these functions. */ |
| 82 | unsigned long io_i915_read32(unsigned long addr); |
| 83 | void io_i915_write32(unsigned long val, unsigned long addr); |
| 84 | |
| 85 | /* |
| 86 | * To communicate to and control the extracted-from-kernel code, |
| 87 | * we need this struct. It has a counterpart in the ARM code, so |
| 88 | * there is a precedent. |
| 89 | */ |
| 90 | |
| 91 | #define DP_RECEIVER_CAP_SIZE 0xf |
| 92 | #define DP_LINK_STATUS_SIZE 6 |
| 93 | #define DP_LINK_CHECK_TIMEOUT (10 * 1000) |
| 94 | |
| 95 | #define DP_LINK_CONFIGURATION_SIZE 9 |
| 96 | |
Furquan Shaikh | 6b19071 | 2013-07-22 16:18:31 -0700 | [diff] [blame] | 97 | struct intel_dp_m_n { |
| 98 | uint32_t tu; |
| 99 | uint32_t gmch_m; |
| 100 | uint32_t gmch_n; |
| 101 | uint32_t link_m; |
| 102 | uint32_t link_n; |
| 103 | }; |
| 104 | |
Ronald G. Minnich | 99451b1 | 2013-06-27 10:42:59 -0700 | [diff] [blame] | 105 | struct intel_dp { |
| 106 | int gen; // 6 for link, 7 for wtm2 |
| 107 | int has_pch_split; // 1 for link and wtm2 |
| 108 | int has_pch_cpt; // 1 for everything we know about. |
| 109 | int is_haswell; |
| 110 | /* output register offset in MMIO space. Usually DP_A */ |
| 111 | u32 output_reg; |
| 112 | /* The initial value of the DP register. |
| 113 | * Mainboards can set this to a non-zero |
| 114 | * value in the case that there are undetectable |
| 115 | * but essential parameters. |
| 116 | */ |
| 117 | u32 DP; |
| 118 | uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE]; |
| 119 | u32 color_range; |
| 120 | /* these paramaters are determined after reading the DPCD */ |
| 121 | int dpms_mode; |
| 122 | uint8_t link_bw; |
| 123 | uint8_t lane_count; |
| 124 | /* This data is read from the panel via the AUX channel.*/ |
| 125 | uint8_t dpcd[DP_RECEIVER_CAP_SIZE]; |
| 126 | int type; |
| 127 | int edp; |
| 128 | int is_pch_edp; |
| 129 | /* state related to training. */ |
| 130 | uint8_t train_set[4]; |
| 131 | /* Determined from EDID or coreboot hard-sets. */ |
| 132 | int panel_power_up_delay; |
| 133 | int panel_power_down_delay; |
| 134 | int panel_power_cycle_delay; |
| 135 | int backlight_on_delay; |
| 136 | int backlight_off_delay; |
| 137 | int want_panel_vdd; |
| 138 | u32 clock; |
| 139 | int port; |
| 140 | int pipe; |
Furquan Shaikh | 77f48cd | 2013-08-19 10:16:50 -0700 | [diff] [blame] | 141 | int plane; |
Ronald G. Minnich | 9518b56 | 2013-09-19 16:45:22 -0700 | [diff] [blame^] | 142 | int pipe_bits_per_pixel; |
Ronald G. Minnich | 99451b1 | 2013-06-27 10:42:59 -0700 | [diff] [blame] | 143 | /* i2c on aux is ... interesting. |
| 144 | * Before you do an i2c cycle, you need to set the address. |
| 145 | * This requires we remember it from one moment to the next. |
| 146 | * Remember it here. |
| 147 | */ |
| 148 | u16 address; |
| 149 | /* timing parameters for aux channel IO. They used to compute these on |
| 150 | * each and every entry to the functions, which is kind of stupid, and it had |
| 151 | * errors anyway. |
| 152 | * note: you can get these from watching YABEL output. E.g.: |
| 153 | * you see an outb of 0x802300e1 to 64010. the 3 is the precharge |
| 154 | * and the e1 is the clock divider. |
| 155 | */ |
| 156 | u32 aux_clock_divider; |
| 157 | u32 precharge; |
| 158 | /* EDID, raw and processed */ |
| 159 | u8 rawedid[256]; |
| 160 | int edidlen; |
| 161 | struct edid edid; |
| 162 | /* computed values needed for "i915" registers */ |
| 163 | int bytes_per_pixel; |
| 164 | u32 htotal; |
| 165 | u32 hblank; |
| 166 | u32 hsync; |
| 167 | u32 vtotal; |
| 168 | u32 vblank; |
| 169 | u32 vsync; |
| 170 | u32 pfa_sz; |
| 171 | u32 pfa_pos; |
| 172 | u32 pfa_ctl; |
| 173 | u32 pipesrc; |
| 174 | u32 stride; |
Furquan Shaikh | 6b19071 | 2013-07-22 16:18:31 -0700 | [diff] [blame] | 175 | struct intel_dp_m_n m_n; |
Furquan Shaikh | d0a81f7 | 2013-07-30 12:41:08 -0700 | [diff] [blame] | 176 | u32 flags; |
Furquan Shaikh | db3157c | 2013-07-31 16:47:31 -0700 | [diff] [blame] | 177 | u32 transcoder; |
Ronald G. Minnich | 99451b1 | 2013-06-27 10:42:59 -0700 | [diff] [blame] | 178 | }; |
| 179 | |
| 180 | /* we may yet need these. */ |
| 181 | void intel_dp_mode_set(struct intel_dp *intel_dp); |
| 182 | void intel_dp_start_link_train(struct intel_dp *intel_dp); |
| 183 | void intel_dp_complete_link_train(struct intel_dp *intel_dp); |
| 184 | void intel_dp_link_down(struct intel_dp *intel_dp); |
| 185 | |
| 186 | int intel_dp_i2c_init(struct intel_dp *intel_dp); |
| 187 | int intel_dp_i2c_aux_ch(struct intel_dp *intel_dp, |
| 188 | int mode, uint8_t write_byte, uint8_t *read_byte); |
| 189 | void |
| 190 | intel_dp_dpms(struct intel_dp *intel_dp, int mode); |
| 191 | |
| 192 | int intel_dp_get_dpcd(struct intel_dp *intel_dp); |
| 193 | struct edid *intel_dp_get_edid(struct intel_dp *intel_dp); |
| 194 | |
| 195 | void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode); |
| 196 | void ironlake_edp_pll_on(void); |
| 197 | void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp); |
| 198 | void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, int sync); |
| 199 | int intel_dp_get_max_downspread(struct intel_dp *intel_dp, u8 *max_downspread); |
| 200 | void ironlake_edp_panel_on(struct intel_dp *intel_dp); |
| 201 | void ironlake_edp_backlight_on(struct intel_dp *intel_dp); |
| 202 | /* needed only on haswell. */ |
Ronald G. Minnich | 99451b1 | 2013-06-27 10:42:59 -0700 | [diff] [blame] | 203 | void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp, int port); |
| 204 | int intel_dp_aux_ch(struct intel_dp *intel_dp, |
| 205 | uint8_t *send, int send_bytes, |
| 206 | uint8_t *recv, int recv_size); |
| 207 | void unpack_aux(u32 src, uint8_t *dst, int dst_bytes); |
| 208 | |
| 209 | |
| 210 | /* drm_dp_helper.c */ |
| 211 | int drm_dp_channel_eq_ok(u8 link_status[DP_LINK_STATUS_SIZE], |
| 212 | int lane_count); |
| 213 | int drm_dp_clock_recovery_ok(u8 link_status[DP_LINK_STATUS_SIZE], |
| 214 | int lane_count); |
| 215 | u8 drm_dp_get_adjust_request_voltage(u8 link_status[DP_LINK_STATUS_SIZE], |
| 216 | int lane); |
| 217 | u8 drm_dp_get_adjust_request_pre_emphasis(u8 link_status[DP_LINK_STATUS_SIZE], |
| 218 | int lane); |
| 219 | |
| 220 | |
Ronald G. Minnich | 45df596 | 2013-07-08 14:02:57 -0700 | [diff] [blame] | 221 | void intel_dp_wait_reg(unsigned long addr, |
| 222 | unsigned long val); |
| 223 | |
| 224 | void intel_dp_wait_panel_power_control(unsigned long val); |
| 225 | |
Furquan Shaikh | 6b19071 | 2013-07-22 16:18:31 -0700 | [diff] [blame] | 226 | void intel_dp_compute_m_n(unsigned int bits_per_pixel, |
| 227 | unsigned int nlanes, |
| 228 | unsigned int pixel_clock, |
| 229 | unsigned int link_clock, |
| 230 | struct intel_dp_m_n *m_n); |
Furquan Shaikh | d0a81f7 | 2013-07-30 12:41:08 -0700 | [diff] [blame] | 231 | |
| 232 | u32 intel_ddi_calc_transcoder_flags(u32 pipe_bpp, |
| 233 | enum port port, |
| 234 | enum pipe pipe, |
| 235 | int type, |
| 236 | int lane_count, |
Furquan Shaikh | 771c3ac | 2013-08-01 13:58:17 -0700 | [diff] [blame] | 237 | int pf_sz, |
| 238 | u8 phsync, |
| 239 | u8 pvsync); |
Furquan Shaikh | db3157c | 2013-07-31 16:47:31 -0700 | [diff] [blame] | 240 | |
| 241 | enum transcoder intel_ddi_get_transcoder(enum port port, |
| 242 | enum pipe pipe); |
| 243 | |
| 244 | void intel_dp_set_m_n_regs(struct intel_dp *intel_dp); |
| 245 | void intel_dp_set_resolution(struct intel_dp *intel_dp); |
Furquan Shaikh | 997be3d | 2013-07-31 13:17:30 -0700 | [diff] [blame] | 246 | |
| 247 | int intel_dp_i2c_write(struct intel_dp *intel_dp, |
| 248 | u8 val); |
| 249 | |
| 250 | int intel_dp_i2c_read(struct intel_dp *intel_dp, |
| 251 | u8 *val); |
| 252 | |
| 253 | int intel_dp_set_bw(struct intel_dp *intel_dp); |
| 254 | int intel_dp_set_lane_count(struct intel_dp *intel_dp); |
| 255 | int intel_dp_set_training_lane0(struct intel_dp *intel_dp, |
| 256 | u8 val); |
| 257 | int intel_dp_set_training_pattern(struct intel_dp *intel_dp, |
| 258 | u8 pat); |
| 259 | |
| 260 | int intel_dp_get_link_status(struct intel_dp *intel_dp, |
| 261 | uint8_t link_status[DP_LINK_STATUS_SIZE]); |
| 262 | |
| 263 | int intel_dp_get_training_pattern(struct intel_dp *intel_dp, |
| 264 | u8 *recv); |
| 265 | |
| 266 | int intel_dp_get_lane_count(struct intel_dp *intel_dp, |
| 267 | u8 *recv); |
| 268 | |
| 269 | int intel_dp_get_lane_align_status(struct intel_dp *intel_dp, |
| 270 | u8 *recv); |
Furquan Shaikh | 77f48cd | 2013-08-19 10:16:50 -0700 | [diff] [blame] | 271 | |
| 272 | void intel_prepare_ddi(void); |
| 273 | void intel_ddi_set_pipe_settings(struct intel_dp *intel_dp); |
| 274 | |
Ronald G. Minnich | 9518b56 | 2013-09-19 16:45:22 -0700 | [diff] [blame^] | 275 | int gtt_poll(u32 reg, u32 mask, u32 value); |
Furquan Shaikh | 77f48cd | 2013-08-19 10:16:50 -0700 | [diff] [blame] | 276 | void gtt_write(u32 reg, u32 data); |
| 277 | u32 gtt_read(u32 reg); |
| 278 | |
| 279 | int i915lightup(unsigned int physbase, unsigned int mmio, |
| 280 | unsigned int gfx, unsigned int init_fb); |