Seunghwan Kim | 6b76edc | 2024-02-02 09:23:16 +0900 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
| 2 | |
| 3 | #include <baseboard/variants.h> |
| 4 | #include <soc/gpio.h> |
| 5 | |
| 6 | static const struct pad_config gpio_overrides[] = { |
| 7 | /* A6 : ESPI_ALERT1# ==> NC */ |
| 8 | PAD_NC(GPP_A6, NONE), |
| 9 | /* A7 : SRCCLK_OE7# ==> PU 100K 3.3V */ |
| 10 | PAD_CFG_GPI(GPP_A7, NONE, DEEP), |
| 11 | /* A8 : SRCCLKREQ7# ==> NC */ |
| 12 | PAD_NC(GPP_A8, NONE), |
| 13 | /* A12 : SATAXPCIE1 ==> NC */ |
| 14 | PAD_NC(GPP_A12, NONE), |
| 15 | /* A14 : USB_OC1# ==> NC */ |
| 16 | PAD_NC(GPP_A14, NONE), |
| 17 | /* A15 : USB_OC2# ==> NC */ |
| 18 | PAD_NC(GPP_A15, NONE), |
| 19 | /* A16 : USB_OC3# ==> NC */ |
| 20 | PAD_NC(GPP_A16, NONE), |
| 21 | /* A17 : DISP_MISCC ==> EN_WCAM_PWR */ |
| 22 | PAD_CFG_GPO(GPP_A17, 1, DEEP), |
| 23 | /* A21 : DDPC_CTRCLK ==> NC */ |
| 24 | PAD_NC(GPP_A21, NONE), |
| 25 | /* A22 : DDPC_CTRLDATA ==> NC */ |
| 26 | PAD_NC(GPP_A22, NONE), |
| 27 | |
| 28 | /* B2 : VRALERT# ==> NC */ |
| 29 | PAD_NC(GPP_B2, NONE), |
| 30 | /* B3 : PROC_GP2 ==> PU 100K 1.8V */ |
| 31 | PAD_CFG_GPI(GPP_B3, NONE, DEEP), |
| 32 | /* B4 : PROC_GP3 ==> NC */ |
| 33 | PAD_NC(GPP_B4, NONE), |
| 34 | /* B5 : ISH_I2C0_SDA ==> NC */ |
| 35 | PAD_NC(GPP_B5, NONE), |
| 36 | /* B6 : ISH_I2C0_SCL ==> NC */ |
| 37 | PAD_NC(GPP_B6, NONE), |
| 38 | /* B7 : ISH_12C1_SDA ==> NC */ |
| 39 | PAD_NC(GPP_B7, NONE), |
| 40 | /* B8 : ISH_I2C1_SCL ==> NC */ |
| 41 | PAD_NC(GPP_B8, NONE), |
| 42 | /* B9 : NC */ |
| 43 | PAD_NC(GPP_B9, NONE), |
| 44 | /* B10 : NC */ |
| 45 | PAD_NC(GPP_B10, NONE), |
| 46 | /* B11 : PMCALERT# ==> NC */ |
| 47 | PAD_NC(GPP_B11, NONE), |
| 48 | /* B15 : TIME_SYNC0 ==> PU 100K 3.3V */ |
| 49 | PAD_CFG_GPI(GPP_B15, NONE, DEEP), |
| 50 | |
| 51 | /* C0 : SMBCLK ==> NC */ |
| 52 | PAD_NC(GPP_C0, NONE), |
| 53 | /* C1 : SMBDATA ==> NC */ |
| 54 | PAD_NC(GPP_C1, NONE), |
| 55 | /* C3 : SML0CLK ==> NC */ |
| 56 | PAD_NC(GPP_C3, NONE), |
| 57 | /* C4 : SML0DATA ==> NC */ |
| 58 | PAD_NC(GPP_C4, NONE), |
| 59 | /* C6 : SML1CLK ==> NC */ |
| 60 | PAD_NC(GPP_C6, NONE), |
| 61 | /* C7 : SML1DATA ==> NC */ |
| 62 | PAD_NC(GPP_C7, NONE), |
| 63 | |
| 64 | /* D0 : ISH_GP0 ==> NC */ |
| 65 | PAD_NC(GPP_D0, NONE), |
| 66 | /* D1 : ISH_GP1 ==> NC */ |
| 67 | PAD_NC(GPP_D1, NONE), |
| 68 | /* D2 : ISH_GP2 ==> NC */ |
| 69 | PAD_NC(GPP_D2, NONE), |
| 70 | /* D3 : ISH_GP3 ==> NC */ |
| 71 | PAD_NC(GPP_D3, NONE), |
| 72 | /* D5 : SRCCLKREQ0# ==> PU 100K 1.8V */ |
| 73 | PAD_CFG_GPI(GPP_D5, NONE, DEEP), |
| 74 | /* D7 : SRCCLKREQ2# ==> NC */ |
| 75 | PAD_NC(GPP_D7, NONE), |
| 76 | /* D8 : SRCCLKREQ3# ==> PU 100K 3.3V */ |
| 77 | PAD_CFG_GPI(GPP_D8, NONE, DEEP), |
| 78 | /* D9 : ISH_SPI_CS# ==> NC */ |
| 79 | PAD_NC(GPP_D9, NONE), |
| 80 | /* D13 : ISH_UART0_RXD ==> NC */ |
| 81 | PAD_NC(GPP_D13, NONE), |
| 82 | /* D14 : ISH_UART0_TXD ==> NC */ |
| 83 | PAD_NC(GPP_D14, NONE), |
| 84 | /* D15 : ISH_UART0_RTS# ==> NC */ |
| 85 | PAD_NC(GPP_D15, NONE), |
| 86 | /* D16 : ISH_UART0_CTS# ==> NC */ |
| 87 | PAD_NC(GPP_D16, NONE), |
| 88 | /* D17 : UART1_RXD ==> PU 100K 3.3V */ |
| 89 | PAD_CFG_GPI(GPP_D17, NONE, DEEP), |
| 90 | /* D18 : UART1_TXD ==> NC */ |
| 91 | PAD_NC(GPP_D18, NONE), |
| 92 | |
| 93 | /* E0 : SATAXPCIE0 ==> NC */ |
| 94 | PAD_NC(GPP_E0, NONE), |
| 95 | /* E3 : PROC_GP0 ==> PU 100K 1.8V */ |
| 96 | PAD_CFG_GPI(GPP_E3, NONE, DEEP), |
| 97 | /* E4 : SATA_DEVSLP0 ==> NC */ |
| 98 | PAD_NC(GPP_E4, NONE), |
| 99 | /* E5 : SATA_DEVSLP1 ==> NC */ |
| 100 | PAD_NC(GPP_E5, NONE), |
| 101 | /* E7 : PROC_GP1 ==> PU 100K 1.8V */ |
| 102 | PAD_CFG_GPI(GPP_E7, NONE, DEEP), |
| 103 | /* E10 : THC0_SPI1_CS# ==> PU 100K 1.8V */ |
| 104 | PAD_CFG_GPI(GPP_E10, NONE, DEEP), |
| 105 | /* E16 : RSVD_TP ==> NC */ |
| 106 | PAD_NC(GPP_E16, NONE), |
| 107 | /* E17 : THC0_SPI1_INT# ==> PU 100K 1.8V */ |
| 108 | PAD_CFG_GPI(GPP_E17, NONE, DEEP), |
| 109 | /* E18 : DDP1_CTRLCLK ==> NC */ |
| 110 | PAD_NC(GPP_E18, NONE), |
| 111 | /* E20 : DDP2_CTRLCLK ==> NC */ |
| 112 | PAD_NC(GPP_E20, NONE), |
| 113 | |
| 114 | /* F6 : CNV_PA_BLANKING ==> NC */ |
| 115 | PAD_NC(GPP_F6, NONE), |
| 116 | /* F11 : THC1_SPI2_CLK ==> NC */ |
| 117 | PAD_NC(GPP_F11, NONE), |
| 118 | /* F12 : GSXDOUT ==> NC */ |
| 119 | PAD_NC(GPP_F12, NONE), |
| 120 | /* F13 : GSXDOUT ==> NC */ |
| 121 | PAD_NC(GPP_F13, NONE), |
| 122 | /* F15 : GSXSRESET# ==> PU 100K 3.3V */ |
| 123 | PAD_CFG_GPI(GPP_F15, NONE, DEEP), |
| 124 | /* F16 : GSXCLK ==> NC */ |
| 125 | PAD_NC(GPP_F16, NONE), |
| 126 | /* F19 : SRCCLKREQ6# ==> NC */ |
| 127 | PAD_NC(GPP_F19, NONE), |
| 128 | /* F20 : EXT_PWR_GATE# ==> NC */ |
| 129 | PAD_NC(GPP_F20, NONE), |
| 130 | /* F21 : EXT_PWR_GATE2# ==> PU 100K 1.8V */ |
| 131 | PAD_CFG_GPI(GPP_F21, NONE, DEEP), |
| 132 | |
| 133 | /* H3 : SX_EXIT_HOLDOFF# ==> NC */ |
| 134 | PAD_NC(GPP_H3, NONE), |
| 135 | /* H8 : I2C4_SDA ==> NC */ |
| 136 | PAD_NC(GPP_H8, NONE), |
| 137 | /* H9 : I2C4_SCL ==> NC */ |
| 138 | PAD_NC(GPP_H9, NONE), |
| 139 | /* H12 : I2C7_SDA ==> PU 100K 3.3V */ |
| 140 | PAD_CFG_GPI(GPP_H12, NONE, DEEP), |
| 141 | /* H13 : I2C7_SCL ==> NC */ |
| 142 | PAD_NC(GPP_H13, NONE), |
| 143 | /* H19 : SRCCLKREQ4# ==> PU 100K 1.8V */ |
| 144 | PAD_CFG_GPI(GPP_H19, NONE, DEEP), |
| 145 | /* H20 : IMGCLKOUT1 ==> NC */ |
| 146 | PAD_NC(GPP_H20, NONE), |
| 147 | /* H21 : IMGCLKOUT2 ==> NC */ |
| 148 | PAD_NC(GPP_H21, NONE), |
| 149 | /* H22 : IMGCLKOUT3 ==> NC */ |
| 150 | PAD_NC(GPP_H22, NONE), |
| 151 | /* H23 : SRCCLKREQ5# ==> PU 100K 3.3V */ |
| 152 | PAD_CFG_GPI(GPP_H23, NONE, DEEP), |
| 153 | |
Seunghwan Kim | f3b2c6e | 2024-03-27 14:47:08 +0900 | [diff] [blame] | 154 | /* R4 : HDA_RST# ==> DMIC_CLK0 */ |
| 155 | PAD_CFG_NF(GPP_R4, NONE, DEEP, NF3), |
| 156 | /* R5 : HDA_SDI1 ==> DMIC_DATA0 */ |
| 157 | PAD_CFG_NF(GPP_R5, NONE, DEEP, NF3), |
| 158 | /* R6 : I2S2_TXD ==> NC */ |
| 159 | PAD_NC(GPP_R6, NONE), |
Seunghwan Kim | 6b76edc | 2024-02-02 09:23:16 +0900 | [diff] [blame] | 160 | /* R7 : I2S2_RXD ==> NC */ |
| 161 | PAD_NC(GPP_R7, NONE), |
| 162 | |
Seunghwan Kim | f3b2c6e | 2024-03-27 14:47:08 +0900 | [diff] [blame] | 163 | /* S0 : SNDW0_CLK ==> SDW_HP_CLK_R */ |
| 164 | PAD_CFG_NF(GPP_S0, NONE, DEEP, NF4), |
| 165 | /* S1 : SNDW0_DATA ==> SDW_HP_DATA_R */ |
| 166 | PAD_CFG_NF(GPP_S1, NONE, DEEP, NF4), |
| 167 | /* S2 : SNDW1_CLK ==> DMIC_CLK0_R */ |
| 168 | PAD_CFG_NF(GPP_S2, NONE, DEEP, NF4), |
| 169 | /* S3 : SNDW1_DATA ==> NC */ |
| 170 | PAD_NC(GPP_S3, NONE), |
Seunghwan Kim | 6b76edc | 2024-02-02 09:23:16 +0900 | [diff] [blame] | 171 | /* S4 : SNDW2_CLK ==> NC */ |
| 172 | PAD_NC(GPP_S4, NONE), |
| 173 | /* S5 : SNDW2_DATA ==> NC */ |
| 174 | PAD_NC(GPP_S5, NONE), |
| 175 | /* S6 : SNDW3_CLK ==> NC */ |
| 176 | PAD_NC(GPP_S6, NONE), |
| 177 | /* S7 : SNDW3_DATA ==> NC */ |
| 178 | PAD_NC(GPP_S7, NONE), |
| 179 | |
| 180 | /* GPD6: SLP_A# ==> NC */ |
| 181 | PAD_NC(GPD6, NONE), |
| 182 | /* GPD8: SUSCLK ==> NC */ |
| 183 | PAD_NC(GPD8, NONE), |
| 184 | /* GPD9: SLP_WLAN# ==> NC */ |
| 185 | PAD_NC(GPD9, NONE), |
| 186 | /* GPD11: LANPHYC ==> NC */ |
| 187 | PAD_NC(GPD11, NONE), |
| 188 | }; |
| 189 | |
| 190 | /* Early pad configuration in bootblock */ |
| 191 | static const struct pad_config early_gpio_table[] = { |
| 192 | /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ |
| 193 | PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), |
| 194 | /* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */ |
| 195 | PAD_CFG_GPI(GPP_E13, NONE, DEEP), |
| 196 | /* E15 : RSVD_TP ==> PCH_WP_OD */ |
| 197 | PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), |
Seunghwan Kim | 9493c2e | 2024-04-29 11:20:50 +0900 | [diff] [blame^] | 198 | /* F18 : EC_IN_RW_OD ==> EC_IN_RW_OD */ |
| 199 | PAD_CFG_GPI(GPP_F18, NONE, DEEP), |
Seunghwan Kim | 6b76edc | 2024-02-02 09:23:16 +0900 | [diff] [blame] | 200 | /* H6 : I2C1_SDA ==> PCH_I2C_TPM_SDA */ |
| 201 | PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), |
| 202 | /* H7 : I2C1_SCL ==> PCH_I2C_TPM_SCL */ |
| 203 | PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), |
| 204 | /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */ |
| 205 | PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), |
| 206 | /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ |
| 207 | PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), |
Seunghwan Kim | cc5cef6 | 2024-03-04 11:36:12 +0900 | [diff] [blame] | 208 | |
| 209 | /* Add virtual GPIOs for CPU PCIe RP */ |
| 210 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, PLTRST, NF1), |
| 211 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, PLTRST, NF1), |
| 212 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, PLTRST, NF1), |
| 213 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, PLTRST, NF1), |
| 214 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, PLTRST, NF1), |
| 215 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, PLTRST, NF1), |
| 216 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, PLTRST, NF1), |
| 217 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, PLTRST, NF1), |
| 218 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, PLTRST, NF1), |
| 219 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, PLTRST, NF1), |
| 220 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, PLTRST, NF1), |
| 221 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, PLTRST, NF1), |
| 222 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, PLTRST, NF1), |
| 223 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, PLTRST, NF1), |
| 224 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, PLTRST, NF1), |
| 225 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, PLTRST, NF1), |
| 226 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, PLTRST, NF1), |
| 227 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, PLTRST, NF1), |
| 228 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, PLTRST, NF1), |
| 229 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, PLTRST, NF1), |
Seunghwan Kim | 6b76edc | 2024-02-02 09:23:16 +0900 | [diff] [blame] | 230 | }; |
| 231 | |
| 232 | const struct pad_config *variant_gpio_override_table(size_t *num) |
| 233 | { |
| 234 | *num = ARRAY_SIZE(gpio_overrides); |
| 235 | return gpio_overrides; |
Seunghwan Kim | 6b76edc | 2024-02-02 09:23:16 +0900 | [diff] [blame] | 236 | } |
| 237 | |
| 238 | const struct pad_config *variant_early_gpio_table(size_t *num) |
| 239 | { |
| 240 | *num = ARRAY_SIZE(early_gpio_table); |
| 241 | return early_gpio_table; |
| 242 | } |