Angel Pons | 182dbde | 2020-04-02 23:49:05 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 2 | |
| 3 | #ifndef SOUTHBRIDGE_INTEL_BD82X6X_CHIP_H |
| 4 | #define SOUTHBRIDGE_INTEL_BD82X6X_CHIP_H |
| 5 | |
Arthur Heymans | ebf201b | 2019-05-28 13:51:36 +0200 | [diff] [blame] | 6 | #include <southbridge/intel/common/spi.h> |
Angel Pons | af4bd56 | 2021-12-28 13:05:56 +0100 | [diff] [blame] | 7 | #include <types.h> |
Keith Hui | 943b540 | 2024-01-22 20:11:24 -0500 | [diff] [blame^] | 8 | #include <southbridge/intel/bd82x6x/pch.h> |
Elyes HAOUAS | c4e4193 | 2018-11-01 11:29:50 +0100 | [diff] [blame] | 9 | |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 10 | struct southbridge_intel_bd82x6x_config { |
| 11 | /** |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 12 | * GPI Routing configuration |
| 13 | * |
| 14 | * Only the lower two bits have a meaning: |
| 15 | * 00: No effect |
| 16 | * 01: SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) |
| 17 | * 10: SCI (if corresponding GPIO_EN bit is also set) |
| 18 | * 11: reserved |
| 19 | */ |
| 20 | uint8_t gpi0_routing; |
| 21 | uint8_t gpi1_routing; |
| 22 | uint8_t gpi2_routing; |
| 23 | uint8_t gpi3_routing; |
| 24 | uint8_t gpi4_routing; |
| 25 | uint8_t gpi5_routing; |
| 26 | uint8_t gpi6_routing; |
| 27 | uint8_t gpi7_routing; |
| 28 | uint8_t gpi8_routing; |
| 29 | uint8_t gpi9_routing; |
| 30 | uint8_t gpi10_routing; |
| 31 | uint8_t gpi11_routing; |
| 32 | uint8_t gpi12_routing; |
| 33 | uint8_t gpi13_routing; |
| 34 | uint8_t gpi14_routing; |
| 35 | uint8_t gpi15_routing; |
| 36 | |
| 37 | uint32_t gpe0_en; |
| 38 | uint16_t alt_gp_smi_en; |
| 39 | |
| 40 | /* IDE configuration */ |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 41 | uint8_t sata_port_map; |
Duncan Laurie | cfb64bd | 2012-07-16 16:16:31 -0700 | [diff] [blame] | 42 | uint32_t sata_port0_gen3_tx; |
| 43 | uint32_t sata_port1_gen3_tx; |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 44 | |
Shawn Nematbakhsh | c9fc029 | 2013-03-14 10:44:13 -0700 | [diff] [blame] | 45 | /** |
| 46 | * SATA Interface Speed Support Configuration |
| 47 | * |
| 48 | * Only the lower two bits have a meaning: |
| 49 | * 00 - No effect (leave as chip default) |
| 50 | * 01 - 1.5 Gb/s maximum speed |
| 51 | * 10 - 3.0 Gb/s maximum speed |
| 52 | * 11 - 6.0 Gb/s maximum speed |
| 53 | */ |
| 54 | uint8_t sata_interface_speed_support; |
| 55 | |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 56 | uint32_t gen1_dec; |
| 57 | uint32_t gen2_dec; |
| 58 | uint32_t gen3_dec; |
| 59 | uint32_t gen4_dec; |
Duncan Laurie | b9fe01c | 2012-04-27 10:30:51 -0700 | [diff] [blame] | 60 | |
| 61 | /* Enable linear PCIe Root Port function numbers starting at zero */ |
Angel Pons | af4bd56 | 2021-12-28 13:05:56 +0100 | [diff] [blame] | 62 | bool pcie_port_coalesce; |
Marc Jones | 4adc8cd | 2012-10-31 16:24:37 -0600 | [diff] [blame] | 63 | |
| 64 | /* Override PCIe ASPM */ |
Angel Pons | 0239684 | 2021-06-05 12:34:23 +0200 | [diff] [blame] | 65 | uint8_t pcie_aspm[8]; |
Vladimir Serbinenko | 5b044ae | 2014-10-25 15:20:55 +0200 | [diff] [blame] | 66 | |
Vladimir Serbinenko | 5b044ae | 2014-10-25 15:20:55 +0200 | [diff] [blame] | 67 | int docking_supported; |
Vladimir Serbinenko | 36fa5b8 | 2014-10-28 23:43:20 +0100 | [diff] [blame] | 68 | |
Felix Singer | f4842bb | 2024-01-12 21:21:06 +0100 | [diff] [blame] | 69 | bool pcie_hotplug_map[8]; |
Vladimir Serbinenko | b26156e | 2015-01-31 17:45:50 +0100 | [diff] [blame] | 70 | |
| 71 | /* Ports which can be routed to either EHCI or xHCI. */ |
| 72 | uint32_t xhci_switchable_ports; |
| 73 | /* Ports which support SuperSpeed (USB 3.0 additional lanes). */ |
| 74 | uint32_t superspeed_capable_ports; |
Nicolas Reinecke | 59aef5c | 2015-04-16 23:25:00 +0200 | [diff] [blame] | 75 | /* Overcurrent Mapping for USB 3.0 Ports */ |
| 76 | uint32_t xhci_overcurrent_mapping; |
Nico Huber | 7b2f9f6 | 2015-10-01 19:00:51 +0200 | [diff] [blame] | 77 | |
| 78 | uint32_t spi_uvscc; |
| 79 | uint32_t spi_lvscc; |
Arthur Heymans | ebf201b | 2019-05-28 13:51:36 +0200 | [diff] [blame] | 80 | struct intel_swseq_spi_config spi; |
Keith Hui | 943b540 | 2024-01-22 20:11:24 -0500 | [diff] [blame^] | 81 | struct southbridge_usb_port usb_port_config[14]; |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 82 | }; |
| 83 | |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 84 | #endif /* SOUTHBRIDGE_INTEL_BD82X6X_CHIP_H */ |