Julius Werner | 028cba9 | 2014-05-30 18:01:44 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright 2014 Google Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | */ |
| 19 | |
Julius Werner | 028cba9 | 2014-05-30 18:01:44 -0700 | [diff] [blame] | 20 | #include <arch/io.h> |
| 21 | #include <console/console.h> |
Julius Werner | 73d1ed6 | 2014-10-20 13:20:49 -0700 | [diff] [blame] | 22 | #include <delay.h> |
| 23 | #include <soc/clock.h> |
| 24 | #include <soc/iomap.h> |
| 25 | #include <soc/usb.h> |
Julius Werner | 028cba9 | 2014-05-30 18:01:44 -0700 | [diff] [blame] | 26 | |
| 27 | #define CRPORT_TX_OVRD_DRV_LO 0x1002 |
| 28 | #define CRPORT_RX_OVRD_IN_HI 0x1006 |
| 29 | #define CRPORT_TX_ALT_BLOCK 0x102d |
| 30 | |
| 31 | static u32 * const tcsr_usb_sel = (void *)0x1a4000b0; |
| 32 | |
| 33 | struct usb_qc_phy { |
| 34 | u32 ipcat; |
| 35 | u32 ctrl; |
| 36 | u32 general_cfg; |
| 37 | u32 ram1; |
| 38 | u32 hs_phy_ctrl; |
| 39 | u32 param_ovrd; |
| 40 | u32 chrg_det_ctrl; |
| 41 | u32 chrg_det_output; |
| 42 | u32 alt_irq_en; |
| 43 | u32 hs_phy_irq_stat; |
| 44 | u32 cgctl; |
| 45 | u32 dbg_bus; |
| 46 | u32 ss_phy_ctrl; |
| 47 | u32 ss_phy_param1; |
| 48 | u32 ss_phy_param2; |
| 49 | u32 crport_data_in; |
| 50 | u32 crport_data_out; |
| 51 | u32 crport_cap_addr; |
| 52 | u32 crport_cap_data; |
| 53 | u32 crport_ack_read; |
| 54 | u32 crport_ack_write; |
| 55 | }; |
| 56 | check_member(usb_qc_phy, crport_ack_write, 0x50); |
| 57 | |
| 58 | static struct usb_qc_phy * const usb_host1_phy = (void *)USB_HOST1_PHY_BASE; |
| 59 | static struct usb_qc_phy * const usb_host2_phy = (void *)USB_HOST2_PHY_BASE; |
| 60 | |
| 61 | struct usb_dwc3 { |
| 62 | u32 sbuscfg0; |
| 63 | u32 sbuscfg1; |
| 64 | u32 txthrcfg; |
| 65 | u32 rxthrcfg; |
| 66 | u32 ctl; |
| 67 | u32 evten; |
| 68 | u32 sts; |
| 69 | u8 reserved0[4]; |
| 70 | u32 snpsid; |
| 71 | u32 gpio; |
| 72 | u32 uid; |
| 73 | u32 uctl; |
| 74 | u64 buserraddr; |
| 75 | u64 prtbimap; |
| 76 | u8 reserved1[32]; |
| 77 | u32 dbgfifospace; |
| 78 | u32 dbgltssm; |
| 79 | u32 dbglnmcc; |
| 80 | u32 dbgbmu; |
| 81 | u32 dbglspmux; |
| 82 | u32 dbglsp; |
| 83 | u32 dbgepinfo0; |
| 84 | u32 dbgepinfo1; |
| 85 | u64 prtbimap_hs; |
| 86 | u64 prtbimap_fs; |
| 87 | u8 reserved2[112]; |
| 88 | u32 usb2phycfg; |
| 89 | u8 reserved3[60]; |
| 90 | u32 usb2i2cctl; |
| 91 | u8 reserved4[60]; |
| 92 | u32 usb2phyacc; |
| 93 | u8 reserved5[60]; |
| 94 | u32 usb3pipectl; |
| 95 | u8 reserved6[60]; |
| 96 | }; |
| 97 | check_member(usb_dwc3, usb3pipectl, 0x1c0); |
| 98 | |
| 99 | static struct usb_dwc3 * const usb_host1_dwc3 = (void *)USB_HOST1_DWC3_BASE; |
| 100 | static struct usb_dwc3 * const usb_host2_dwc3 = (void *)USB_HOST2_DWC3_BASE; |
| 101 | |
| 102 | static void setup_dwc3(struct usb_dwc3 *dwc3) |
| 103 | { |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 104 | write32(&dwc3->usb3pipectl, |
Julius Werner | 9418476 | 2015-02-19 20:19:23 -0800 | [diff] [blame^] | 105 | 0x1 << 31 | /* assert PHY soft reset */ |
| 106 | 0x1 << 25 | /* (default) U1/U2 exit fail -> recovery? */ |
| 107 | 0x1 << 24 | /* (default) activate PHY low power states */ |
| 108 | 0x1 << 19 | /* (default) PHY low power delay value */ |
| 109 | 0x1 << 18 | /* (default) activate PHY low power delay */ |
| 110 | 0x1 << 1 | /* (default) Tx deemphasis value */ |
| 111 | 0x1 << 0); /* (default) elastic buffer mode */ |
Julius Werner | 028cba9 | 2014-05-30 18:01:44 -0700 | [diff] [blame] | 112 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 113 | write32(&dwc3->usb2phycfg, |
Julius Werner | 9418476 | 2015-02-19 20:19:23 -0800 | [diff] [blame^] | 114 | 0x1 << 31 | /* assert PHY soft reset */ |
| 115 | 0x9 << 10 | /* (default) PHY clock turnaround 8-bit UTMI+ */ |
| 116 | 0x1 << 8 | /* (default) enable PHY sleep in L1 */ |
| 117 | 0x1 << 6); /* (default) enable PHY suspend */ |
Julius Werner | 028cba9 | 2014-05-30 18:01:44 -0700 | [diff] [blame] | 118 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 119 | write32(&dwc3->ctl, |
Julius Werner | 9418476 | 2015-02-19 20:19:23 -0800 | [diff] [blame^] | 120 | 0x2 << 19 | /* (default) suspend clock scaling */ |
| 121 | 0x1 << 16 | /* retry SS three times before HS downgrade */ |
| 122 | 0x1 << 12 | /* port capability HOST */ |
| 123 | 0x1 << 11 | /* assert core soft reset */ |
| 124 | 0x1 << 10 | /* (default) sync ITP to refclk */ |
| 125 | 0x1 << 2); /* U2 exit after 8us LFPS (instead of 248ns) */ |
Julius Werner | 028cba9 | 2014-05-30 18:01:44 -0700 | [diff] [blame] | 126 | |
Julius Werner | 9418476 | 2015-02-19 20:19:23 -0800 | [diff] [blame^] | 127 | write32(&dwc3->uctl, |
| 128 | 0x32 << 22 | /* (default) reference clock period in ns */ |
| 129 | 0x1 << 15 | /* (default) XHCI compliant device addressing */ |
| 130 | 0x10 << 0); /* (default) devices time out after 32us */ |
Julius Werner | 028cba9 | 2014-05-30 18:01:44 -0700 | [diff] [blame] | 131 | |
| 132 | udelay(5); |
| 133 | |
| 134 | clrbits_le32(&dwc3->ctl, 0x1 << 11); /* deassert core soft reset */ |
| 135 | clrbits_le32(&dwc3->usb2phycfg, 0x1 << 31); /* PHY soft reset */ |
| 136 | clrbits_le32(&dwc3->usb3pipectl, 0x1 << 31); /* PHY soft reset */ |
| 137 | } |
| 138 | |
| 139 | static void setup_phy(struct usb_qc_phy *phy) |
| 140 | { |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 141 | write32(&phy->ss_phy_ctrl, |
Julius Werner | 9418476 | 2015-02-19 20:19:23 -0800 | [diff] [blame^] | 142 | 0x1 << 24 | /* Indicate VBUS power present */ |
| 143 | 0x1 << 8 | /* Enable USB3 ref clock to prescaler */ |
| 144 | 0x1 << 7 | /* assert SS PHY reset */ |
| 145 | 0x19 << 0); /* (default) reference clock multiplier */ |
Julius Werner | 028cba9 | 2014-05-30 18:01:44 -0700 | [diff] [blame] | 146 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 147 | write32(&phy->hs_phy_ctrl, |
Julius Werner | 9418476 | 2015-02-19 20:19:23 -0800 | [diff] [blame^] | 148 | 0x1 << 26 | /* (default) unclamp DPSE/DMSE VLS */ |
| 149 | 0x1 << 25 | /* (default) select freeclk for utmi_clk */ |
| 150 | 0x1 << 24 | /* (default) unclamp DMSE VLS */ |
| 151 | 0x1 << 21 | /* (default) enable UTMI clock */ |
| 152 | 0x1 << 20 | /* set OTG VBUS as valid */ |
| 153 | 0x1 << 18 | /* use ref clock from core */ |
| 154 | 0x1 << 17 | /* (default) unclamp DPSE VLS */ |
| 155 | 0x1 << 11 | /* force xo/bias/pll to stay on in suspend */ |
| 156 | 0x1 << 9 | /* (default) unclamp IDHV */ |
| 157 | 0x1 << 8 | /* (default) unclamp VLS (again???) */ |
| 158 | 0x1 << 7 | /* (default) unclamp HV VLS */ |
| 159 | 0x7 << 4 | /* select frequency (no idea which one) */ |
| 160 | 0x1 << 1); /* (default) "retention enable" */ |
Julius Werner | 028cba9 | 2014-05-30 18:01:44 -0700 | [diff] [blame] | 161 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 162 | write32(&phy->ss_phy_param1, |
Julius Werner | 9418476 | 2015-02-19 20:19:23 -0800 | [diff] [blame^] | 163 | 0x6e << 20 | /* full TX swing amplitude */ |
| 164 | 0x20 << 14 | /* (default) 6dB TX deemphasis */ |
| 165 | 0x17 << 8 | /* 3.5dB TX deemphasis */ |
| 166 | 0x9 << 3); /* (default) LoS detector level */ |
Julius Werner | 028cba9 | 2014-05-30 18:01:44 -0700 | [diff] [blame] | 167 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 168 | write32(&phy->general_cfg, 0x1 << 2); /* set XHCI 1.00 compliance */ |
Julius Werner | 028cba9 | 2014-05-30 18:01:44 -0700 | [diff] [blame] | 169 | |
| 170 | udelay(5); |
| 171 | clrbits_le32(&phy->ss_phy_ctrl, 0x1 << 7); /* deassert SS PHY reset */ |
| 172 | } |
| 173 | |
| 174 | static void crport_handshake(void *capture_reg, void *acknowledge_bit, u32 data) |
| 175 | { |
| 176 | int usec = 100; |
| 177 | |
| 178 | if (capture_reg) |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 179 | write32(capture_reg, data); |
Julius Werner | 028cba9 | 2014-05-30 18:01:44 -0700 | [diff] [blame] | 180 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 181 | write32(acknowledge_bit, 0x1 << 0); |
Julius Werner | 028cba9 | 2014-05-30 18:01:44 -0700 | [diff] [blame] | 182 | while (read32(acknowledge_bit) && --usec) |
| 183 | udelay(1); |
| 184 | |
| 185 | if (!usec) |
| 186 | printk(BIOS_ERR, "CRPORT handshake timed out (0x%08x)\n", data); |
| 187 | } |
| 188 | |
| 189 | static void crport_write(struct usb_qc_phy *phy, u16 addr, u16 data) |
| 190 | { |
| 191 | crport_handshake(&phy->crport_data_in, &phy->crport_cap_addr, addr); |
| 192 | crport_handshake(&phy->crport_data_in, &phy->crport_cap_data, data); |
| 193 | crport_handshake(NULL, &phy->crport_ack_write, 0); |
| 194 | } |
| 195 | |
| 196 | static void tune_phy(struct usb_qc_phy *phy) |
| 197 | { |
| 198 | crport_write(phy, CRPORT_RX_OVRD_IN_HI, |
| 199 | 0x1 << 11 | /* Set RX_EQ override? */ |
| 200 | 0x4 << 8 | /* Set RX_EQ to 4? */ |
| 201 | 0x1 << 7); /* Enable RX_EQ override */ |
| 202 | crport_write(phy, CRPORT_TX_OVRD_DRV_LO, |
| 203 | 0x1 << 14 | /* Enable amplitude (override?) */ |
| 204 | 0x17 << 7 | /* Set TX deemphasis to 23 */ |
| 205 | 0x6e << 0); /* Set amplitude to 110 */ |
| 206 | crport_write(phy, CRPORT_TX_ALT_BLOCK, |
| 207 | 0x1 << 7); /* ALT block? ("partial RX reset") */ |
| 208 | } |
| 209 | |
| 210 | void setup_usb_host1(void) |
| 211 | { |
| 212 | printk(BIOS_INFO, "Setting up USB HOST1 controller...\n"); |
| 213 | setbits_le32(tcsr_usb_sel, 1 << 0); /* Select DWC3 controller */ |
| 214 | setup_phy(usb_host1_phy); |
| 215 | setup_dwc3(usb_host1_dwc3); |
| 216 | tune_phy(usb_host1_phy); |
| 217 | } |
| 218 | |
| 219 | void setup_usb_host2(void) |
| 220 | { |
| 221 | printk(BIOS_INFO, "Setting up USB HOST2 controller...\n"); |
| 222 | setbits_le32(tcsr_usb_sel, 1 << 1); /* Select DWC3 controller */ |
| 223 | setup_phy(usb_host2_phy); |
| 224 | setup_dwc3(usb_host2_dwc3); |
| 225 | tune_phy(usb_host2_phy); |
| 226 | } |