blob: 1992664944a107af97581def9855ee34ad7c1d10 [file] [log] [blame]
Stefan Reinauerb7ecf6d2013-03-13 17:13:32 -07001chip northbridge/intel/sandybridge
Vladimir Serbinenkodd2bc3f2014-10-31 09:16:31 +01002 # IGD Displays
3 register "gfx.ndid" = "3"
4 register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }"
Stefan Reinauerb7ecf6d2013-03-13 17:13:32 -07005
6 # Enable DisplayPort Hotplug with 6ms pulse
7 register "gpu_dp_d_hotplug" = "0x06"
8
9 # Enable Panel as LVDS and configure power delays
10 register "gpu_panel_port_select" = "0" # LVDS
11 register "gpu_panel_power_cycle_delay" = "5" # T4: 400ms
12 register "gpu_panel_power_up_delay" = "400" # T1+T2: 40ms
13 register "gpu_panel_power_down_delay" = "150" # T3: 15ms
14 register "gpu_panel_power_backlight_on_delay" = "2100" # T5: 210ms
15 register "gpu_panel_power_backlight_off_delay" = "2100" # TD: 210ms
16
17 device cpu_cluster 0 on
18 chip cpu/intel/socket_rPGA989
19 device lapic 0 on end
20 end
21 chip cpu/intel/model_206ax
22 # Magic APIC ID to locate this chip
23 device lapic 0xACAC off end
24
Stefan Reinauerb7ecf6d2013-03-13 17:13:32 -070025 register "tcc_offset" = "5" # TCC of 95C
26
27 register "c1_acpower" = "1" # ACPI(C1) = MWAIT(C1)
28 register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3)
29 register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7)
30
31 register "c1_battery" = "1" # ACPI(C1) = MWAIT(C1)
32 register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3)
33 register "c3_battery" = "5" # ACPI(C3) = MWAIT(C7)
34 end
35 end
36
37 device domain 0 on
38 subsystemid 0x1ae0 0xc000 inherit
39 device pci 00.0 on end # host bridge
40 device pci 02.0 on end # vga controller
41
42 chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
Stefan Reinauerb7ecf6d2013-03-13 17:13:32 -070043 # GPI routing
44 # 0 No effect (default)
45 # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
46 # 2 SCI (if corresponding GPIO_EN bit is also set)
47 register "alt_gp_smi_en" = "0x0002"
48 register "gpi1_routing" = "1"
49 register "gpi6_routing" = "2"
50
Stefan Reinauerb7ecf6d2013-03-13 17:13:32 -070051 register "sata_port_map" = "0x3"
Shawn Nematbakhsh7b8952c2013-03-14 11:03:59 -070052 # Set max SATA speed to 3.0 Gb/s
53 register "sata_interface_speed_support" = "0x2"
Stefan Reinauerb7ecf6d2013-03-13 17:13:32 -070054
55 # Enable EC Port 0x68/0x6C
56 register "gen1_dec" = "0x00040069"
57
58 # EC range is 0x800-0x9ff
59 register "gen2_dec" = "0x00fc0901"
60
61 # EC range is 0x1610-0x161F
62 register "gen3_dec" = "0x0001C1611"
63
64 # Enable zero-based linear PCIe root port functions
65 register "pcie_port_coalesce" = "1"
66
Vladimir Serbinenko5b044ae2014-10-25 15:20:55 +020067 register "c2_latency" = "1"
68 register "p_cnt_throttling_supported" = "0"
69
Stefan Reinauerb7ecf6d2013-03-13 17:13:32 -070070 device pci 14.0 on end # USB 3.0 Controller
71 device pci 16.0 on end # Management Engine Interface 1
72 device pci 16.1 off end # Management Engine Interface 2
73 device pci 16.2 off end # Management Engine IDE-R
74 device pci 16.3 off end # Management Engine KT
75 device pci 19.0 off end # Intel Gigabit Ethernet
76 device pci 1a.0 on end # USB2 EHCI #2 (AUO4, BlueTooth)
77 device pci 1b.0 on end # High Definition Audio
78 device pci 1c.0 on end # PCIe Port #1
79 device pci 1c.1 on end # PCIe Port #2 (WLAN)
80 device pci 1c.2 on end # PCIe Port #3 (Card Reader)
81 register "pcie_aspm_f2" = "0x3"
82 device pci 1c.3 off end # PCIe Port #4
83 device pci 1c.4 off end # PCIe Port #5
84 device pci 1c.5 on end # PCIe Port #6 (LAN)
85 device pci 1c.6 off end # PCIe Port #7
86 device pci 1c.7 off end # PCIe Port #8
87 device pci 1d.0 on end # USB2 EHCI #1 (Camera, WLAN, WWAN)
88 device pci 1e.0 off end # PCI bridge
89 device pci 1f.0 on
90 chip ec/quanta/it8518
91 # 60h/64h KBC
92 device pnp ff.1 on # dummy address
93 end
94 end
95 end # LPC bridge
96 device pci 1f.2 on end # SATA Controller 1 (HDD/SSD)
97 device pci 1f.3 on end # SMBus Controller
98 device pci 1f.5 off end # SATA Controller 2 (MSATA)
99 device pci 1f.6 off end # Thermal
100 end
101 end
102end