Jonathan Zhang | 9355bc0 | 2023-01-04 12:23:11 -0800 | [diff] [blame^] | 1 | /** |
| 2 | Copyright (c) 2019-2021, Intel Corporation. All rights reserved.<BR> |
| 3 | |
| 4 | Redistribution and use in source and binary forms, with or without modification, |
| 5 | are permitted provided that the following conditions are met: |
| 6 | |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | list of conditions and the following disclaimer. |
| 9 | * Redistributions in binary form must reproduce the above copyright notice, this |
| 10 | list of conditions and the following disclaimer in the documentation and/or |
| 11 | other materials provided with the distribution. |
| 12 | * Neither the name of Intel Corporation nor the names of its contributors may |
| 13 | be used to endorse or promote products derived from this software without |
| 14 | specific prior written permission. |
| 15 | |
| 16 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 17 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 18 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 19 | ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE |
| 20 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 21 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 22 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 23 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 24 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 25 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF |
| 26 | THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | |
| 28 | **/ |
| 29 | |
| 30 | |
| 31 | #ifndef _HOB_IIOUDS_H_ |
| 32 | #define _HOB_IIOUDS_H_ |
| 33 | |
| 34 | #include <fsp/util.h> |
| 35 | |
| 36 | #include "defs_iio.h" |
| 37 | #include "IioUniversalDataHob.h" |
| 38 | |
| 39 | #define FSP_HOB_IIO_UNIVERSAL_DATA_GUID { \ |
| 40 | 0xa1, 0x96, 0xf3, 0x7f, 0x7d, 0xee, 0x1e, 0x43, \ |
| 41 | 0xba, 0x53, 0x8f, 0xCa, 0x12, 0x7c, 0x44, 0xc0 \ |
| 42 | } |
| 43 | |
| 44 | #define NUMBER_PORTS_PER_SOCKET MAX_IIO_PORTS_PER_SOCKET |
| 45 | |
| 46 | #pragma pack(1) |
| 47 | |
| 48 | /** |
| 49 | * IIO Stacks |
| 50 | * |
| 51 | * Ports(XCC) Stack(HOB) IioConfigIou |
| 52 | * ========================================= |
| 53 | * 0 stack 0 DmiAsPcie |
| 54 | * 1A..1H stack 1 IOU0 |
| 55 | * 2A..2H stack 2 IOU1 |
| 56 | * 3A..3H stack 3 IOU2 |
| 57 | * 4A..4H stack 4 IOU3 |
| 58 | * 5A..5H stack 5 IOU4 |
| 59 | * 6A..6H stack 6 IOU5 |
| 60 | */ |
| 61 | |
| 62 | /** |
| 63 | IIO PCIe Ports |
| 64 | **/ |
| 65 | |
| 66 | typedef enum { |
| 67 | // DmiAsPcie, stack 0 |
| 68 | PORT_0 = 0, |
| 69 | // IOU0, stack 1 |
| 70 | PORT_1A, |
| 71 | PORT_1B, |
| 72 | PORT_1C, |
| 73 | PORT_1D, |
| 74 | PORT_1E, |
| 75 | PORT_1F, |
| 76 | PORT_1G, |
| 77 | PORT_1H, |
| 78 | // IOU1, stack 2 |
| 79 | PORT_2A, |
| 80 | PORT_2B, |
| 81 | PORT_2C, |
| 82 | PORT_2D, |
| 83 | PORT_2E, |
| 84 | PORT_2F, |
| 85 | PORT_2G, |
| 86 | PORT_2H, |
| 87 | // IOU2, stack 3 |
| 88 | PORT_3A, |
| 89 | PORT_3B, |
| 90 | PORT_3C, |
| 91 | PORT_3D, |
| 92 | PORT_3E, |
| 93 | PORT_3F, |
| 94 | PORT_3G, |
| 95 | PORT_3H, |
| 96 | // IOU3, stack 4 |
| 97 | PORT_4A, |
| 98 | PORT_4B, |
| 99 | PORT_4C, |
| 100 | PORT_4D, |
| 101 | PORT_4E, |
| 102 | PORT_4F, |
| 103 | PORT_4G, |
| 104 | PORT_4H, |
| 105 | // IOU4, stack 5 |
| 106 | PORT_5A, |
| 107 | PORT_5B, |
| 108 | PORT_5C, |
| 109 | PORT_5D, |
| 110 | PORT_5E, |
| 111 | PORT_5F, |
| 112 | PORT_5G, |
| 113 | PORT_5H, |
| 114 | // IOU5, stack 6, not used for socket 0; for socket 1, swap from DMI as x8 |
| 115 | PORT_6A, |
| 116 | PORT_6B, |
| 117 | PORT_6C, |
| 118 | PORT_6D, |
| 119 | PORT_6E, |
| 120 | PORT_6F, |
| 121 | PORT_6G, |
| 122 | PORT_6H, |
| 123 | // IOU6, stack 7, not used |
| 124 | PORT_7A, |
| 125 | PORT_7B, |
| 126 | PORT_7C, |
| 127 | PORT_7D, |
| 128 | PORT_7E, |
| 129 | PORT_7F, |
| 130 | PORT_7G, |
| 131 | PORT_7H, |
| 132 | |
| 133 | MAX_PORTS |
| 134 | } PCIE_PORTS; |
| 135 | |
| 136 | typedef enum { |
| 137 | //for ICX |
| 138 | IioStack0 = 0, // DmiAsPcie |
| 139 | IioStack1 = 1, // IOU0 |
| 140 | IioStack2 = 2, // IOU1 |
| 141 | IioStack3 = 3, // IOU2 |
| 142 | IioStack4 = 4, // IOU3 |
| 143 | IioStack5 = 5, // IOU4 |
| 144 | //for SPR |
| 145 | IioStack6 = 6, // IOU5 |
| 146 | IioStack7 = 7, |
| 147 | IioStack8 = 8, |
| 148 | IioStack9 = 9, |
| 149 | IioStack10 = 10, |
| 150 | IioStack11 = 11, |
| 151 | //for later SOC |
| 152 | IioStack12 = 12, |
| 153 | IioStack13 = 13, |
| 154 | IioStack14 = 14, |
| 155 | IioStack15 = 15, |
| 156 | IioStack16 = 16, |
| 157 | IioStack17 = 17, |
| 158 | IioStack18 = 18, |
| 159 | IioStackUnknown = 0xFF |
| 160 | } IIO_STACK; |
| 161 | |
| 162 | typedef enum { |
| 163 | TYPE_UBOX = 0, |
| 164 | TYPE_UBOX_IIO, |
| 165 | TYPE_MCP, |
| 166 | TYPE_FPGA, |
| 167 | TYPE_HFI, |
| 168 | TYPE_NAC, |
| 169 | TYPE_GRAPHICS, |
| 170 | TYPE_DINO, |
| 171 | TYPE_RESERVED, |
| 172 | TYPE_DISABLED, // This item must be prior to stack specific disable types |
| 173 | TYPE_UBOX_IIO_DIS, |
| 174 | TYPE_MCP_DIS, |
| 175 | TYPE_FPGA_DIS, |
| 176 | TYPE_HFI_DIS, |
| 177 | TYPE_NAC_DIS, |
| 178 | TYPE_GRAPHICS_DIS, |
| 179 | TYPE_DINO_DIS, |
| 180 | TYPE_RESERVED_DIS, |
| 181 | TYPE_NONE |
| 182 | } STACK_TYPE; |
| 183 | |
| 184 | #pragma pack() |
| 185 | |
| 186 | #endif |