| Jonathan Zhang | 9355bc0 | 2023-01-04 12:23:11 -0800 | [diff] [blame^] | 1 | /** @file |
| 2 | |
| 3 | Copyright (c) 2021, Intel Corporation. All rights reserved.<BR> |
| 4 | |
| 5 | Redistribution and use in source and binary forms, with or without modification, |
| 6 | are permitted provided that the following conditions are met: |
| 7 | |
| 8 | * Redistributions of source code must retain the above copyright notice, this |
| 9 | list of conditions and the following disclaimer. |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, this |
| 11 | list of conditions and the following disclaimer in the documentation and/or |
| 12 | other materials provided with the distribution. |
| 13 | * Neither the name of Intel Corporation nor the names of its contributors may |
| 14 | be used to endorse or promote products derived from this software without |
| 15 | specific prior written permission. |
| 16 | |
| 17 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 18 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 19 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 20 | ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE |
| 21 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 22 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 23 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 24 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 25 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 26 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF |
| 27 | THE POSSIBILITY OF SUCH DAMAGE. |
| 28 | |
| 29 | **/ |
| 30 | |
| 31 | #ifndef __DEFS_MEMMAP_H__ |
| 32 | #define __DEFS_MEMMAP_H__ |
| 33 | |
| 34 | /* Bit definitions for RasModes */ |
| 35 | #define CH_INDEPENDENT 0 |
| 36 | #define FULL_MIRROR_1LM BIT0 |
| 37 | #define FULL_MIRROR_2LM BIT1 |
| 38 | #define CH_LOCKSTEP BIT2 |
| 39 | #define RK_SPARE BIT3 |
| 40 | #define PARTIAL_MIRROR_1LM BIT5 |
| 41 | #define PARTIAL_MIRROR_2LM BIT6 |
| 42 | #define STAT_VIRT_LOCKSTEP BIT7 |
| 43 | |
| 44 | #define MEMTYPE_1LM_MASK (1 << 0) |
| 45 | #define MEMTYPE_2LM_MASK (1 << 1) |
| 46 | #define MEMTYPE_VOLATILE_MASK (MEMTYPE_1LM_MASK | MEMTYPE_2LM_MASK) |
| 47 | |
| 48 | /* ACPI SRAT Memory Flags */ |
| 49 | #define SRAT_ACPI_MEMORY_ENABLED (1 << 0) |
| 50 | #define SRAT_ACPI_MEMORY_HOT_REMOVE_SUPPORTED (1 << 1) |
| 51 | #define SRAT_ACPI_MEMORY_NONVOLATILE (1 << 2) |
| 52 | |
| 53 | #define MEM_TYPE_RESERVED (1 << 8) |
| 54 | #define MEM_ADDR_64MB_SHIFT_BITS 26 |
| 55 | |
| 56 | //------------------------------------------------------------------------------------ |
| 57 | // Uncomment line(s) below to override macro definitions in FSP MemoryMapDataHob.h |
| 58 | //------------------------------------------------------------------------------------ |
| 59 | // #define MAX_UNIQUE_NGN_DIMM_INTERLEAVE 2 |
| 60 | // #define MAX_SPARE_RANK 2 |
| 61 | // #define MAX_SOCKET 4 // Potentially need to refactor |
| 62 | // #define MAX_IMC 4 // Potentially need to refactor |
| 63 | // #define MAX_HBM_IO 4 |
| 64 | // #define MAX_MC_CH 2 |
| 65 | // #define MAX_DIMM 2 // Max DIMM per channel |
| 66 | // #define MAX_RANK_DIMM 2 |
| 67 | // #define MAX_DRAM_CLUSTERS 4 |
| 68 | // #define MAX_SAD_RULES 16 |
| 69 | // #define MAX_FPGA_REMOTE_SAD_RULES 2 // Maximum FPGA sockets exists on ICX platform |
| 70 | |
| 71 | #endif |