| Jonathan Zhang | 9355bc0 | 2023-01-04 12:23:11 -0800 | [diff] [blame^] | 1 | /** @file |
| 2 | |
| 3 | @copyright |
| 4 | INTEL CONFIDENTIAL |
| 5 | Copyright 2007 -2021 Intel Corporation. <BR> |
| 6 | |
| 7 | The source code contained or described herein and all documents related to the |
| 8 | source code ("Material") are owned by Intel Corporation or its suppliers or |
| 9 | licensors. Title to the Material remains with Intel Corporation or its suppliers |
| 10 | and licensors. The Material may contain trade secrets and proprietary and |
| 11 | confidential information of Intel Corporation and its suppliers and licensors, |
| 12 | and is protected by worldwide copyright and trade secret laws and treaty |
| 13 | provisions. No part of the Material may be used, copied, reproduced, modified, |
| 14 | published, uploaded, posted, transmitted, distributed, or disclosed in any way |
| 15 | without Intel's prior express written permission. |
| 16 | |
| 17 | No license under any patent, copyright, trade secret or other intellectual |
| 18 | property right is granted to or conferred upon you by disclosure or delivery |
| 19 | of the Materials, either expressly, by implication, inducement, estoppel or |
| 20 | otherwise. Any license under such intellectual property rights must be |
| 21 | express and approved by Intel in writing. |
| 22 | |
| 23 | Unless otherwise agreed by Intel in writing, you may not remove or alter |
| 24 | this notice or any other notice embedded in Materials by Intel or |
| 25 | Intel's suppliers or licensors in any way. |
| 26 | **/ |
| 27 | |
| 28 | #ifndef _PREV_BOOT_ERR_SRC_HOB_H_ |
| 29 | #define _PREV_BOOT_ERR_SRC_HOB_H_ |
| 30 | |
| 31 | #define FSP_PREV_BOOT_ERR_SRC_HOB_GUID \ |
| 32 | { 0xc5, 0xb5, 0x38, 0x51, 0x69, 0x93, 0xec, 0x48, 0x5b, 0x97, 0x38, 0xa2, 0xf7, 0x09, 0x66, 0x75 } |
| 33 | |
| 34 | #define PREV_BOOT_ERR_SRC_HOB_SIZE 1000 |
| 35 | |
| 36 | #pragma pack(1) |
| 37 | |
| 38 | typedef struct { |
| 39 | UINT16 Length; // Actual size of the error sources used in the HOB |
| 40 | UINT8 HobData[PREV_BOOT_ERR_SRC_HOB_SIZE -2]; // List of Error source structures of format //MCBANK_ERR_INFO or CSR_ERR_INFO |
| 41 | }PREV_BOOT_ERR_SRC_HOB; |
| 42 | |
| 43 | typedef struct{ |
| 44 | UINT8 Type; // McBankType = 1; |
| 45 | UINT8 Segment; |
| 46 | UINT8 Socket; |
| 47 | UINT16 ApicId; // ApicId is Needed only if it a core McBank. |
| 48 | UINT16 McBankNum; |
| 49 | UINT64 McBankStatus; |
| 50 | UINT64 McbankAddr; |
| 51 | UINT64 McBankMisc; |
| 52 | } MCBANK_ERR_INFO; |
| 53 | |
| 54 | typedef struct { |
| 55 | UINT8 Type; // PciExType =2 ; |
| 56 | UINT8 Segment; |
| 57 | UINT8 Bus; |
| 58 | UINT8 Device; |
| 59 | UINT8 Function; |
| 60 | UINT32 AerUncErrSts; |
| 61 | UINT8 AerHdrLogData[16]; |
| 62 | } PCI_EX_ERR_INFO; |
| 63 | |
| 64 | typedef struct { |
| 65 | UINT8 Type; // Other Csr error type =3 ; |
| 66 | UINT8 Segment; |
| 67 | UINT8 Bus; |
| 68 | UINT8 Device; |
| 69 | UINT8 Function; |
| 70 | UINT16 offset; |
| 71 | UINT32 Value; |
| 72 | } CSR_ERR_INFO; |
| 73 | |
| 74 | typedef enum { |
| 75 | McBankType = 1, |
| 76 | PciExType, |
| 77 | CsrOtherType |
| 78 | } ERROR_ACCESS_TYPE; |
| 79 | |
| 80 | #pragma pack() |
| 81 | |
| 82 | #endif //_PREV_BOOT_ERR_SRC_HOB_H_ |