Jonathan Zhang | 9355bc0 | 2023-01-04 12:23:11 -0800 | [diff] [blame^] | 1 | /** @file |
| 2 | Header file to define the structures used for FSPM dynamic configuration. |
| 3 | |
| 4 | @copyright |
| 5 | INTEL CONFIDENTIAL |
| 6 | Copyright 2021 Intel Corporation. <BR> |
| 7 | |
| 8 | The source code contained or described herein and all documents related to the |
| 9 | source code ("Material") are owned by Intel Corporation or its suppliers or |
| 10 | licensors. Title to the Material remains with Intel Corporation or its suppliers |
| 11 | and licensors. The Material may contain trade secrets and proprietary and |
| 12 | confidential information of Intel Corporation and its suppliers and licensors, |
| 13 | and is protected by worldwide copyright and trade secret laws and treaty |
| 14 | provisions. No part of the Material may be used, copied, reproduced, modified, |
| 15 | published, uploaded, posted, transmitted, distributed, or disclosed in any way |
| 16 | without Intel's prior express written permission. |
| 17 | |
| 18 | No license under any patent, copyright, trade secret or other intellectual |
| 19 | property right is granted to or conferred upon you by disclosure or delivery |
| 20 | of the Materials, either expressly, by implication, inducement, estoppel or |
| 21 | otherwise. Any license under such intellectual property rights must be |
| 22 | express and approved by Intel in writing. |
| 23 | |
| 24 | Unless otherwise agreed by Intel in writing, you may not remove or alter |
| 25 | this notice or any other notice embedded in Materials by Intel or |
| 26 | Intel's suppliers or licensors in any way. |
| 27 | **/ |
| 28 | |
| 29 | #ifndef _IIO_PCIE_CONFIG_UPD_H_ |
| 30 | #define _IIO_PCIE_CONFIG_UPD_H_ |
| 31 | |
| 32 | #ifndef MAX_SOCKET |
| 33 | #define MAX_SOCKET 4 |
| 34 | #endif |
| 35 | |
| 36 | #ifndef MAX_LOGIC_IIO_STACK |
| 37 | #define MAX_LOGIC_IIO_STACK 14 |
| 38 | #endif |
| 39 | |
| 40 | #ifndef MAX_IIO_PORTS_PER_SOCKET |
| 41 | #define MAX_IIO_PORTS_PER_SOCKET 57 |
| 42 | #endif |
| 43 | |
| 44 | #ifndef MAX_IOU_PER_SOCKET |
| 45 | #define MAX_IOU_PER_SOCKET 7 |
| 46 | #endif |
| 47 | |
| 48 | #define MAX_VMD_STACKS_PER_SOCKET 8 // Max number of stacks per socket supported by VMD |
| 49 | |
| 50 | #pragma pack(1) |
| 51 | |
| 52 | typedef struct { |
| 53 | UINT8 SLOTEIP[MAX_IIO_PORTS_PER_SOCKET]; // Electromechanical Interlock Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B17) |
| 54 | UINT8 SLOTHPCAP[MAX_IIO_PORTS_PER_SOCKET]; // Slot Hot Plug capable - Slot Capabilities (D0-10 / F0 / R0xA4 / B6) |
| 55 | UINT8 SLOTHPSUP[MAX_IIO_PORTS_PER_SOCKET]; // Hot Plug surprise supported - Slot Capabilities (D0-10 / F0 / R0xA4 / B5) |
| 56 | UINT8 SLOTPIP[MAX_IIO_PORTS_PER_SOCKET]; // Power Indicator Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B4) |
| 57 | UINT8 SLOTAIP[MAX_IIO_PORTS_PER_SOCKET]; // Attention Inductor Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B3) |
| 58 | UINT8 SLOTMRLSP[MAX_IIO_PORTS_PER_SOCKET]; // MRL Sensor Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B2) |
| 59 | UINT8 SLOTPCP[MAX_IIO_PORTS_PER_SOCKET]; // Power Controller Present - Slot Capabilities (D0-10 / F0 / R0xA4 /B1) |
| 60 | UINT8 SLOTABP[MAX_IIO_PORTS_PER_SOCKET]; // Attention Button Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B0) |
| 61 | UINT8 SLOTIMP[MAX_IIO_PORTS_PER_SOCKET]; |
| 62 | UINT8 SLOTSPLS[MAX_IIO_PORTS_PER_SOCKET]; |
| 63 | UINT8 SLOTSPLV[MAX_IIO_PORTS_PER_SOCKET]; |
| 64 | UINT16 SLOTPSP[MAX_IIO_PORTS_PER_SOCKET]; |
| 65 | BOOLEAN VppEnabled[MAX_IIO_PORTS_PER_SOCKET]; // 00 -- Disable, 01 -- Enable //no setup option defined- aj |
| 66 | UINT8 VppPort[MAX_IIO_PORTS_PER_SOCKET]; // 00 -- Port 0, 01 -- Port 1 //no setup option defined- aj |
| 67 | UINT8 VppAddress[MAX_IIO_PORTS_PER_SOCKET]; // 01-07 for SMBUS address of Vpp //no setup option defined- aj |
| 68 | UINT8 MuxAddress[MAX_IIO_PORTS_PER_SOCKET]; // SMBUS address of MUX //no setup option defined |
| 69 | UINT8 ChannelID[MAX_IIO_PORTS_PER_SOCKET]; // 00 -- channel 0, 01 -- channel 1 //no setup option defined |
| 70 | |
| 71 | UINT8 PciePortEnable[MAX_IIO_PORTS_PER_SOCKET]; |
| 72 | UINT8 PEXPHIDE[MAX_IIO_PORTS_PER_SOCKET]; // Hide any of the DMI or PCIE devices - SKT 0,1,2,3; Device 0-10 PRD |
| 73 | UINT8 HidePEXPMenu[MAX_IIO_PORTS_PER_SOCKET]; // to suppress /display the PCIe port menu |
| 74 | UINT8 PciePortOwnership[MAX_IIO_PORTS_PER_SOCKET]; |
| 75 | UINT8 RetimerConnectCount[MAX_IIO_PORTS_PER_SOCKET]; |
| 76 | UINT8 ConfigIOU[MAX_IOU_PER_SOCKET]; // 00-x4x4x4x4, 01-x4x4x8NA, 02-x8NAx4x4, 03-x8NAx8NA, 04-x16 (P1p2p3p4) |
| 77 | UINT8 PcieHotPlugOnPort[MAX_IIO_PORTS_PER_SOCKET]; // Manual override of hotplug for port |
| 78 | UINT8 VMDEnabled[MAX_VMD_STACKS_PER_SOCKET]; |
| 79 | UINT8 VMDPortEnable[MAX_IIO_PORTS_PER_SOCKET]; |
| 80 | UINT8 VMDHotPlugEnable[MAX_VMD_STACKS_PER_SOCKET]; |
| 81 | UINT8 PcieMaxPayload[MAX_IIO_PORTS_PER_SOCKET]; |
| 82 | UINT8 PciePortLinkSpeed[MAX_IIO_PORTS_PER_SOCKET]; // auto - 0(default); gen1 -1; gen2 -2; ... gen5 -5. |
| 83 | UINT8 DfxDnTxPresetGen3[MAX_IIO_PORTS_PER_SOCKET]; //auto - 0xFF(default); p0 - 0; p1 -1; ... p9 - 9. |
| 84 | UINT8 PcieGlobalAspm; |
| 85 | UINT8 PcieMaxReadRequestSize; |
| 86 | } UPD_IIO_PCIE_PORT_CONFIG; |
| 87 | |
| 88 | typedef struct { |
| 89 | struct { |
| 90 | UINT8 Segment; ///< Remember segment, if it changes reset everything |
| 91 | UINT8 StackPciBusPoolSize[MAX_LOGIC_IIO_STACK]; ///< Number of bus numbers needed for IIO stack |
| 92 | } Socket[MAX_SOCKET]; |
| 93 | } SYSTEM_PCI_BUS_CONFIGURATION; |
| 94 | |
| 95 | typedef struct { |
| 96 | UINT64 Base; ///< Base (starting) address of a range (I/O, 32 and 64-bit mmio regions) |
| 97 | UINT64 Limit; ///< Limit (last valid) address of a range |
| 98 | } PCIE_BASE_LIMIT; |
| 99 | |
| 100 | typedef struct { |
| 101 | UINT32 MmioLSize; |
| 102 | UINT64 MmioHSize; |
| 103 | } CXL11_LIMITS; |
| 104 | |
| 105 | typedef struct { |
| 106 | PCIE_BASE_LIMIT Io; ///< Base and limit of I/O range assigned to entity |
| 107 | PCIE_BASE_LIMIT LowMmio; ///< Base and limit of low MMIO region for entity |
| 108 | PCIE_BASE_LIMIT HighMmio; ///< Base and limit of high (64-bit) MMIO region for entity |
| 109 | } PCI_BASE_LIMITS; |
| 110 | |
| 111 | typedef struct { |
| 112 | PCI_BASE_LIMITS SocketLimits; ///< Base and Limit of all PCIe resources for the socket |
| 113 | PCI_BASE_LIMITS StackLimits[MAX_LOGIC_IIO_STACK]; ///< Base and Limit of all PCIe resources for each stack of the socket |
| 114 | CXL11_LIMITS CxlStackReq[MAX_LOGIC_IIO_STACK]; ///< Base and Limit of CXL11 resources for each stack of the socket |
| 115 | } SOCKET_PCI_BASE_LIMITS; |
| 116 | |
| 117 | typedef struct { |
| 118 | // |
| 119 | // Save basic system configuration parameters along with the resource map to detect a change. |
| 120 | // Remember low and high I/O memory range when saving recource configuration. It is used to verify |
| 121 | // whether system memory map changed. Remember also stacks configured when creating the map. |
| 122 | // If anything changed reset the system PCI resource configuration. |
| 123 | // |
| 124 | UINT64 MmioHBase; |
| 125 | UINT64 MmioHGranularity; |
| 126 | UINT32 MmioLBase; |
| 127 | UINT32 MmioLLimit; |
| 128 | UINT32 MmioLGranularity; |
| 129 | UINT16 IoBase; |
| 130 | UINT16 IoLimit; |
| 131 | UINT16 IoGranularity; |
| 132 | UINT32 StackPresentBitmap[MAX_SOCKET]; |
| 133 | // |
| 134 | // Used by the PciHostBridge DXE driver, these variables don't need to be exposed through setup options |
| 135 | // The variables are used as a communication vehicle from the PciHostBridge DXE driver to an OEM hook |
| 136 | // which updates the KTI resource map. |
| 137 | // |
| 138 | SOCKET_PCI_BASE_LIMITS Socket[MAX_SOCKET]; ///< Base and limit of all PCIe resources for each socket |
| 139 | } SYSTEM_PCI_BASE_LIMITS; |
| 140 | |
| 141 | #pragma pack() |
| 142 | |
| 143 | #endif // _IIO_PCIE_CONFIG_UPD_H_ |