| Tim Crawford | 930dbc0 | 2023-05-16 12:41:31 -0600 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | #include <soc/meminit.h> |
| 4 | #include <soc/romstage.h> |
| 5 | |
| 6 | void mainboard_memory_init_params(FSPM_UPD *mupd) |
| 7 | { |
| 8 | const struct mb_cfg board_cfg = { |
| 9 | .type = MEM_TYPE_DDR5, |
| 10 | .ect = true, |
| 11 | .LpDdrDqDqsReTraining = 1, |
| 12 | }; |
| 13 | const struct mem_spd spd_info = { |
| 14 | .topo = MEM_TOPO_DIMM_MODULE, |
| 15 | .smbus = { |
| 16 | [0] = { .addr_dimm[0] = 0x50, }, |
| 17 | [1] = { .addr_dimm[0] = 0x52, }, |
| 18 | }, |
| 19 | }; |
| 20 | const bool half_populated = false; |
| 21 | |
| 22 | // Set primary display to internal graphics |
| 23 | mupd->FspmConfig.PrimaryDisplay = 0; |
| 24 | |
| 25 | mupd->FspmConfig.DmiMaxLinkSpeed = 4; |
| 26 | mupd->FspmConfig.GpioOverride = 0; |
| 27 | |
| 28 | memcfg_init(mupd, &board_cfg, &spd_info, half_populated); |
| 29 | } |