Mark Hsieh | 19fc004 | 2023-06-28 16:36:28 +0800 | [diff] [blame] | 1 | fw_config |
Mark Hsieh | 2cd2263 | 2023-08-24 20:07:57 +0800 | [diff] [blame] | 2 | field DB_USB 0 1 |
| 3 | option DB_ABSENT 0 |
| 4 | option DB_1C 1 |
| 5 | end |
Mark Hsieh | 7333901 | 2023-08-01 19:16:36 +0800 | [diff] [blame] | 6 | field THERMAL 2 2 |
| 7 | option THERMAL_FANLESS 0 |
| 8 | option THERMAL_FAN 1 |
| 9 | end |
Mark Hsieh | 19fc004 | 2023-06-28 16:36:28 +0800 | [diff] [blame] | 10 | field WIFI_SAR_ID 6 6 |
| 11 | option WIFI_GFP2_SAR_ID_0 0 |
| 12 | option WIFI_GFP2_SAR_ID_1 1 |
| 13 | end |
| 14 | end |
| 15 | |
Mark Hsieh | 24f7554 | 2022-06-15 17:50:22 +0800 | [diff] [blame] | 16 | chip soc/intel/alderlake |
Mark Hsieh | 69bf58d | 2022-07-05 20:53:56 +0800 | [diff] [blame] | 17 | register "sagv" = "SaGv_Enabled" |
Mark Hsieh | 24f7554 | 2022-06-15 17:50:22 +0800 | [diff] [blame] | 18 | |
Mark Hsieh | 90f8151 | 2023-10-05 21:36:38 +0800 | [diff] [blame] | 19 | # Acoustic settings |
| 20 | register "acoustic_noise_mitigation" = "1" |
| 21 | register "slow_slew_rate[VR_DOMAIN_IA]" = "SLEW_FAST_8" |
| 22 | register "slow_slew_rate[VR_DOMAIN_GT]" = "SLEW_FAST_8" |
| 23 | register "fast_pkg_c_ramp_disable[VR_DOMAIN_IA]" = "1" |
| 24 | register "fast_pkg_c_ramp_disable[VR_DOMAIN_GT]" = "1" |
| 25 | |
Chia-Ling Hou | 6f5ead1 | 2023-08-07 15:52:48 +0800 | [diff] [blame] | 26 | # EMMC Tx CMD Delay |
| 27 | # Refer to EDS-Vol2-42.3.7. |
| 28 | # [14:8] steps of delay for DDR mode, each 125ps, range: 0 - 39. |
| 29 | # [6:0] steps of delay for SDR mode, each 125ps, range: 0 - 39. |
| 30 | register "common_soc_config.emmc_dll.emmc_tx_cmd_cntl" = "0x505" |
| 31 | |
| 32 | # EMMC TX DATA Delay 1 |
| 33 | # Refer to EDS-Vol2-42.3.8. |
| 34 | # [14:8] steps of delay for HS400, each 125ps, range: 0 - 78. |
| 35 | # [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79. |
| 36 | register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x909" |
| 37 | |
| 38 | # EMMC TX DATA Delay 2 |
| 39 | # Refer to EDS-Vol2-42.3.9. |
| 40 | # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 79. |
| 41 | # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. |
| 42 | # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79. |
| 43 | # [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79. |
| 44 | register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C272828" |
| 45 | |
| 46 | # EMMC RX CMD/DATA Delay 1 |
| 47 | # Refer to EDS-Vol2-42.3.10. |
| 48 | # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 119. |
| 49 | # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. |
| 50 | # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119. |
| 51 | # [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119. |
| 52 | register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C171733" |
| 53 | |
| 54 | # EMMC RX CMD/DATA Delay 2 |
| 55 | # Refer to EDS-Vol2-42.3.12. |
| 56 | # [17:16] stands for Rx Clock before Output Buffer, |
| 57 | # 00: Rx clock after output buffer, |
| 58 | # 01: Rx clock before output buffer, |
| 59 | # 10: Automatic selection based on working mode. |
| 60 | # 11: Reserved |
| 61 | # [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39. |
| 62 | # [6:0] steps of delay for HS200, each 125ps, range: 0 - 79. |
| 63 | register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x10028" |
| 64 | |
| 65 | # EMMC Rx Strobe Delay |
| 66 | # Refer to EDS-Vol2-42.3.11. |
| 67 | # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps, range: 0 - 39. |
| 68 | # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39. |
| 69 | register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x1414" |
| 70 | |
Mark Hsieh | 69bf58d | 2022-07-05 20:53:56 +0800 | [diff] [blame] | 71 | # Bit 0 - C0 has no redriver, so enable SBU muxing in the SoC. |
| 72 | # Bit 2 - C1 has a redriver which does SBU muxing. |
| 73 | # Bit 1,3 - AUX lines are not swapped on the motherboard for either C0 or C1. |
| 74 | register "tcss_aux_ori" = "1" |
Mark Hsieh | 24f7554 | 2022-06-15 17:50:22 +0800 | [diff] [blame] | 75 | |
Mark Hsieh | 69bf58d | 2022-07-05 20:53:56 +0800 | [diff] [blame] | 76 | register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}" |
| 77 | |
| 78 | register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # UFC |
| 79 | register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for PCIe WLAN |
| 80 | register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for CNVi WLAN |
| 81 | |
Mark Hsieh | 623e3a3 | 2023-06-06 20:13:17 +0800 | [diff] [blame] | 82 | # Configure external V1P05/Vnn/VnnSx Rails |
| 83 | register "ext_fivr_settings" = "{ |
| 84 | .configure_ext_fivr = 1, |
Mark Hsieh | 623e3a3 | 2023-06-06 20:13:17 +0800 | [diff] [blame] | 85 | }" |
| 86 | |
Mark Hsieh | 69bf58d | 2022-07-05 20:53:56 +0800 | [diff] [blame] | 87 | # Intel Common SoC Config |
| 88 | #+-------------------+---------------------------+ |
| 89 | #| Field | Value | |
| 90 | #+-------------------+---------------------------+ |
| 91 | #| I2C0 | TPM. Early init is | |
| 92 | #| | required to set up a BAR | |
| 93 | #| | for TPM communication | |
| 94 | #| I2C1 | Touchscreen | |
| 95 | #| I2C2 | Sub-board(PSensor)/WCAM | |
| 96 | #| I2C3 | Audio | |
| 97 | #| I2C5 | Trackpad | |
| 98 | #+-------------------+---------------------------+ |
| 99 | register "common_soc_config" = "{ |
| 100 | .i2c[0] = { |
| 101 | .early_init = 1, |
Mark Hsieh | 0177c95 | 2023-10-04 18:20:35 +0800 | [diff] [blame] | 102 | .speed = I2C_SPEED_FAST_PLUS, |
| 103 | .speed_config[0] = { |
| 104 | .speed = I2C_SPEED_FAST_PLUS, |
| 105 | .scl_lcnt = 56, |
| 106 | .scl_hcnt = 30, |
| 107 | .sda_hold = 7, |
| 108 | } |
| 109 | }, |
| 110 | .i2c[1] = { |
| 111 | .speed = I2C_SPEED_FAST, |
| 112 | .speed_config[0] = { |
| 113 | .speed = I2C_SPEED_FAST, |
| 114 | .scl_lcnt = 158, |
| 115 | .scl_hcnt = 79, |
| 116 | .sda_hold = 30, |
| 117 | } |
| 118 | }, |
| 119 | .i2c[3] = { |
Mark Hsieh | 69bf58d | 2022-07-05 20:53:56 +0800 | [diff] [blame] | 120 | .speed = I2C_SPEED_FAST, |
| 121 | .speed_config[0] = { |
| 122 | .speed = I2C_SPEED_FAST, |
| 123 | .scl_lcnt = 158, |
| 124 | .scl_hcnt = 79, |
| 125 | .sda_hold = 7, |
| 126 | } |
| 127 | }, |
Mark Hsieh | 69bf58d | 2022-07-05 20:53:56 +0800 | [diff] [blame] | 128 | .i2c[5] = { |
| 129 | .speed = I2C_SPEED_FAST, |
| 130 | .speed_config[0] = { |
| 131 | .speed = I2C_SPEED_FAST, |
Mark Hsieh | 0177c95 | 2023-10-04 18:20:35 +0800 | [diff] [blame] | 132 | .scl_lcnt = 158, |
Mark Hsieh | 69bf58d | 2022-07-05 20:53:56 +0800 | [diff] [blame] | 133 | .scl_hcnt = 79, |
Mark Hsieh | 0177c95 | 2023-10-04 18:20:35 +0800 | [diff] [blame] | 134 | .sda_hold = 40, |
Mark Hsieh | 69bf58d | 2022-07-05 20:53:56 +0800 | [diff] [blame] | 135 | } |
| 136 | }, |
| 137 | }" |
| 138 | |
Mark Hsieh | 926be77 | 2023-10-25 18:11:58 +0800 | [diff] [blame^] | 139 | # Power limit config |
| 140 | |
| 141 | register "power_limits_config[ADL_N_081_15W_CORE]" = "{ |
| 142 | .tdp_pl1_override = 20, |
| 143 | .tdp_pl2_override = 35, |
| 144 | .tdp_pl4 = 83, |
| 145 | }" |
| 146 | register "power_limits_config[ADL_N_041_6W_CORE]" = "{ |
| 147 | .tdp_pl1_override = 10, |
| 148 | .tdp_pl2_override = 25, |
| 149 | .tdp_pl4 = 78, |
| 150 | }" |
| 151 | |
| 152 | register "power_limits_config[ADL_N_021_6W_CORE]" = "{ |
| 153 | .tdp_pl1_override = 10, |
| 154 | .tdp_pl2_override = 25, |
| 155 | .tdp_pl4 = 78, |
| 156 | }" |
| 157 | |
Mark Hsieh | 69bf58d | 2022-07-05 20:53:56 +0800 | [diff] [blame] | 158 | device domain 0 on |
| 159 | device ref dtt on |
| 160 | chip drivers/intel/dptf |
| 161 | ## sensor information |
| 162 | register "options.tsr[0].desc" = ""Memory"" |
| 163 | register "options.tsr[1].desc" = ""Charger"" |
| 164 | register "options.tsr[2].desc" = ""Ambient"" |
| 165 | |
| 166 | # TODO: below values are initial reference values only |
| 167 | ## Passive Policy |
| 168 | register "policies.passive" = "{ |
| 169 | [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000), |
Mark Hsieh | 7333901 | 2023-08-01 19:16:36 +0800 | [diff] [blame] | 170 | [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 65, 5000), |
| 171 | [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 65, 5000), |
| 172 | [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 65, 5000), |
Mark Hsieh | 69bf58d | 2022-07-05 20:53:56 +0800 | [diff] [blame] | 173 | }" |
| 174 | |
| 175 | ## Critical Policy |
| 176 | register "policies.critical" = "{ |
| 177 | [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), |
Mark Hsieh | 7333901 | 2023-08-01 19:16:36 +0800 | [diff] [blame] | 178 | [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 75, SHUTDOWN), |
| 179 | [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 75, SHUTDOWN), |
| 180 | [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 75, SHUTDOWN), |
Mark Hsieh | 69bf58d | 2022-07-05 20:53:56 +0800 | [diff] [blame] | 181 | }" |
| 182 | |
| 183 | register "controls.power_limits" = "{ |
| 184 | .pl1 = { |
Mark Hsieh | 7333901 | 2023-08-01 19:16:36 +0800 | [diff] [blame] | 185 | .min_power = 6000, |
Mark Hsieh | 69bf58d | 2022-07-05 20:53:56 +0800 | [diff] [blame] | 186 | .max_power = 6000, |
| 187 | .time_window_min = 28 * MSECS_PER_SEC, |
| 188 | .time_window_max = 32 * MSECS_PER_SEC, |
| 189 | .granularity = 200 |
| 190 | }, |
| 191 | .pl2 = { |
| 192 | .min_power = 25000, |
| 193 | .max_power = 25000, |
| 194 | .time_window_min = 28 * MSECS_PER_SEC, |
| 195 | .time_window_max = 32 * MSECS_PER_SEC, |
| 196 | .granularity = 1000 |
| 197 | } |
| 198 | }" |
| 199 | |
| 200 | ## Charger Performance Control (Control, mA) |
| 201 | register "controls.charger_perf" = "{ |
| 202 | [0] = { 255, 1700 }, |
| 203 | [1] = { 24, 1500 }, |
| 204 | [2] = { 16, 1000 }, |
| 205 | [3] = { 8, 500 } |
| 206 | }" |
| 207 | |
Mark Hsieh | 7333901 | 2023-08-01 19:16:36 +0800 | [diff] [blame] | 208 | register "oem_data.oem_variables" = "{ |
| 209 | [1] = 0x1 |
| 210 | }" |
| 211 | |
| 212 | device generic 0 alias dptf_policy on end |
Mark Hsieh | 69bf58d | 2022-07-05 20:53:56 +0800 | [diff] [blame] | 213 | end |
| 214 | end |
| 215 | device ref i2c1 on |
Mark Hsieh | aec6f06 | 2023-06-16 19:16:02 +0800 | [diff] [blame] | 216 | chip drivers/i2c/generic |
| 217 | register "hid" = ""ELAN0001"" |
| 218 | register "desc" = ""ELAN Touchscreen"" |
| 219 | register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" |
| 220 | register "detect" = "1" |
| 221 | register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" |
| 222 | register "reset_delay_ms" = "20" |
| 223 | register "reset_off_delay_ms" = "2" |
| 224 | register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)" |
| 225 | register "stop_delay_ms" = "280" |
| 226 | register "stop_off_delay_ms" = "2" |
| 227 | register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" |
| 228 | register "enable_delay_ms" = "1" |
| 229 | register "has_power_resource" = "1" |
| 230 | device i2c 10 on end |
| 231 | end |
| 232 | chip drivers/i2c/hid |
| 233 | register "generic.hid" = ""ELAN2513"" |
| 234 | register "generic.desc" = ""ELAN Touchscreen"" |
| 235 | register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" |
| 236 | register "generic.detect" = "1" |
| 237 | register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" |
| 238 | register "generic.reset_delay_ms" = "20" |
| 239 | register "generic.reset_off_delay_ms" = "2" |
| 240 | register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)" |
| 241 | register "generic.stop_delay_ms" = "280" |
| 242 | register "generic.stop_off_delay_ms" = "2" |
| 243 | register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" |
| 244 | register "generic.enable_delay_ms" = "1" |
| 245 | register "generic.has_power_resource" = "1" |
| 246 | register "hid_desc_reg_offset" = "0x01" |
| 247 | device i2c 15 on end |
| 248 | end |
| 249 | chip drivers/i2c/hid |
| 250 | register "generic.hid" = ""GTCH7503"" |
| 251 | register "generic.desc" = ""G2TOUCH Touchscreen"" |
| 252 | register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" |
| 253 | register "generic.detect" = "1" |
| 254 | register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" |
| 255 | register "generic.reset_delay_ms" = "50" |
| 256 | register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)" |
| 257 | register "generic.stop_delay_ms" = "30" |
| 258 | register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" |
| 259 | register "generic.enable_delay_ms" = "1" |
| 260 | register "generic.has_power_resource" = "1" |
| 261 | register "hid_desc_reg_offset" = "0x01" |
| 262 | device i2c 40 on end |
| 263 | end |
Mark Hsieh | 69bf58d | 2022-07-05 20:53:56 +0800 | [diff] [blame] | 264 | chip drivers/i2c/hid |
| 265 | register "generic.hid" = ""GDIX0000"" |
| 266 | register "generic.desc" = ""Goodix Touchscreen"" |
| 267 | register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" |
Mark Hsieh | aec6f06 | 2023-06-16 19:16:02 +0800 | [diff] [blame] | 268 | register "generic.detect" = "1" |
Mark Hsieh | 69bf58d | 2022-07-05 20:53:56 +0800 | [diff] [blame] | 269 | register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" |
| 270 | register "generic.enable_delay_ms" = "20" |
| 271 | register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" |
| 272 | register "generic.reset_delay_ms" = "180" |
| 273 | register "generic.reset_off_delay_ms" = "3" |
| 274 | register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)" |
| 275 | register "generic.stop_off_delay_ms" = "1" |
| 276 | register "generic.has_power_resource" = "1" |
| 277 | register "hid_desc_reg_offset" = "0x01" |
Mark Hsieh | f84f3e7 | 2022-07-27 21:20:30 +0800 | [diff] [blame] | 278 | device i2c 0x14 on end |
Mark Hsieh | 69bf58d | 2022-07-05 20:53:56 +0800 | [diff] [blame] | 279 | end |
| 280 | end |
| 281 | device ref i2c3 on |
| 282 | chip drivers/i2c/generic |
| 283 | register "hid" = ""RTL5682"" |
| 284 | register "name" = ""RT58"" |
| 285 | register "desc" = ""Headset Codec"" |
| 286 | register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)" |
| 287 | # Set the jd_src to RT5668_JD1 for jack detection |
| 288 | register "property_count" = "1" |
| 289 | register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" |
| 290 | register "property_list[0].name" = ""realtek,jd-src"" |
| 291 | register "property_list[0].integer" = "1" |
| 292 | device i2c 1a on end |
| 293 | end |
| 294 | end |
| 295 | device ref i2c5 on |
| 296 | chip drivers/i2c/generic |
| 297 | register "hid" = ""ELAN0000"" |
| 298 | register "desc" = ""ELAN Touchpad"" |
| 299 | register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)" |
| 300 | register "wake" = "GPE0_DW2_14" |
Matt DeVillier | 2cf52d8 | 2022-09-01 15:09:24 -0500 | [diff] [blame] | 301 | register "detect" = "1" |
Mark Hsieh | 69bf58d | 2022-07-05 20:53:56 +0800 | [diff] [blame] | 302 | device i2c 15 on end |
| 303 | end |
| 304 | end |
| 305 | device ref hda on |
| 306 | chip drivers/generic/max98357a |
| 307 | register "hid" = ""MX98360A"" |
| 308 | register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)" |
| 309 | register "sdmode_delay" = "5" |
| 310 | device generic 0 on end |
| 311 | end |
Matt DeVillier | 189da31 | 2023-09-08 20:57:55 -0500 | [diff] [blame] | 312 | chip drivers/sof |
| 313 | register "spkr_tplg" = "max98360a" |
| 314 | register "jack_tplg" = "rt5682" |
| 315 | register "mic_tplg" = "_2ch_pdm0" |
| 316 | device generic 0 on end |
| 317 | end |
Mark Hsieh | 69bf58d | 2022-07-05 20:53:56 +0800 | [diff] [blame] | 318 | end |
| 319 | device ref pcie_rp4 on |
| 320 | # PCIe 4 WLAN |
| 321 | register "pch_pcie_rp[PCH_RP(4)]" = "{ |
| 322 | .clk_src = 2, |
| 323 | .clk_req = 2, |
| 324 | .flags = PCIE_RP_LTR | PCIE_RP_AER, |
| 325 | }" |
| 326 | chip drivers/wifi/generic |
| 327 | register "wake" = "GPE0_DW1_03" |
Kapil Porwal | da1a58a | 2022-11-23 19:17:35 +0530 | [diff] [blame] | 328 | register "add_acpi_dma_property" = "true" |
Mark Hsieh | 69bf58d | 2022-07-05 20:53:56 +0800 | [diff] [blame] | 329 | device pci 00.0 on end |
| 330 | end |
| 331 | end |
Mark Hsieh | 4b18984 | 2023-06-06 15:00:06 +0800 | [diff] [blame] | 332 | device ref pcie_rp7 off end # PCIE7 no SD card |
Mark Hsieh | 07046ca | 2023-06-12 16:26:54 +0800 | [diff] [blame] | 333 | device ref emmc on end |
Mark Hsieh | 7fb661f | 2023-06-12 17:47:07 +0800 | [diff] [blame] | 334 | device ref ish on |
| 335 | chip drivers/intel/ish |
| 336 | register "add_acpi_dma_property" = "true" |
| 337 | device generic 0 on end |
| 338 | end |
| 339 | end |
Mark Hsieh | 07046ca | 2023-06-12 16:26:54 +0800 | [diff] [blame] | 340 | device ref ufs on end |
Mark Hsieh | 69bf58d | 2022-07-05 20:53:56 +0800 | [diff] [blame] | 341 | device ref pch_espi on |
| 342 | chip ec/google/chromeec |
| 343 | use conn0 as mux_conn[0] |
| 344 | use conn1 as mux_conn[1] |
| 345 | device pnp 0c09.0 on end |
| 346 | end |
| 347 | end |
| 348 | device ref pmc hidden |
| 349 | chip drivers/intel/pmc_mux |
| 350 | device generic 0 on |
| 351 | chip drivers/intel/pmc_mux/conn |
| 352 | use usb2_port1 as usb2_port |
| 353 | use tcss_usb3_port1 as usb3_port |
| 354 | device generic 0 alias conn0 on end |
| 355 | end |
| 356 | chip drivers/intel/pmc_mux/conn |
| 357 | use usb2_port2 as usb2_port |
| 358 | use tcss_usb3_port2 as usb3_port |
| 359 | device generic 1 alias conn1 on end |
| 360 | end |
| 361 | end |
| 362 | end |
| 363 | end |
| 364 | device ref tcss_xhci on |
| 365 | chip drivers/usb/acpi |
| 366 | device ref tcss_root_hub on |
| 367 | chip drivers/usb/acpi |
| 368 | register "desc" = ""USB3 Type-C Port C0 (MLB)"" |
| 369 | register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" |
| 370 | register "use_custom_pld" = "true" |
| 371 | register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" |
| 372 | device ref tcss_usb3_port1 on end |
| 373 | end |
| 374 | chip drivers/usb/acpi |
| 375 | register "desc" = ""USB3 Type-C Port C1 (DB)"" |
| 376 | register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" |
| 377 | register "use_custom_pld" = "true" |
| 378 | register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))" |
Mark Hsieh | 2cd2263 | 2023-08-24 20:07:57 +0800 | [diff] [blame] | 379 | device ref tcss_usb3_port2 on |
| 380 | probe DB_USB DB_1C |
| 381 | end |
Mark Hsieh | 69bf58d | 2022-07-05 20:53:56 +0800 | [diff] [blame] | 382 | end |
| 383 | end |
| 384 | end |
| 385 | end |
| 386 | device ref xhci on |
| 387 | chip drivers/usb/acpi |
| 388 | device ref xhci_root_hub on |
| 389 | chip drivers/usb/acpi |
| 390 | register "desc" = ""USB2 Type-C Port C0 (MLB)"" |
| 391 | register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" |
| 392 | register "use_custom_pld" = "true" |
| 393 | register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" |
| 394 | device ref usb2_port1 on end |
| 395 | end |
| 396 | chip drivers/usb/acpi |
| 397 | register "desc" = ""USB2 Type-C Port C1 (DB)"" |
| 398 | register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" |
| 399 | register "use_custom_pld" = "true" |
| 400 | register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))" |
Mark Hsieh | 2cd2263 | 2023-08-24 20:07:57 +0800 | [diff] [blame] | 401 | device ref usb2_port2 on |
| 402 | probe DB_USB DB_1C |
| 403 | end |
Mark Hsieh | 69bf58d | 2022-07-05 20:53:56 +0800 | [diff] [blame] | 404 | end |
| 405 | chip drivers/usb/acpi |
| 406 | register "desc" = ""USB2 Type-A Port A0 (MLB)"" |
| 407 | register "type" = "UPC_TYPE_A" |
| 408 | register "use_custom_pld" = "true" |
| 409 | register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))" |
| 410 | device ref usb2_port3 on end |
| 411 | end |
| 412 | chip drivers/usb/acpi |
| 413 | register "desc" = ""USB2 UFC"" |
| 414 | register "type" = "UPC_TYPE_INTERNAL" |
| 415 | device ref usb2_port7 on end |
| 416 | end |
| 417 | chip drivers/usb/acpi |
| 418 | register "desc" = ""USB2 Bluetooth"" |
| 419 | register "type" = "UPC_TYPE_INTERNAL" |
| 420 | register "reset_gpio" = |
| 421 | "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)" |
| 422 | device ref usb2_port8 on end |
| 423 | end |
| 424 | chip drivers/usb/acpi |
| 425 | register "desc" = ""CNVi Bluetooth"" |
| 426 | register "type" = "UPC_TYPE_INTERNAL" |
| 427 | register "reset_gpio" = |
| 428 | "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)" |
| 429 | device ref usb2_port10 on end |
| 430 | end |
| 431 | chip drivers/usb/acpi |
| 432 | register "desc" = ""USB3 Type-A Port A0 (MLB)"" |
| 433 | register "type" = "UPC_TYPE_USB3_A" |
| 434 | register "use_custom_pld" = "true" |
| 435 | register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))" |
| 436 | device ref usb3_port1 on end |
| 437 | end |
| 438 | end |
| 439 | end |
| 440 | end |
| 441 | end |
Mark Hsieh | 24f7554 | 2022-06-15 17:50:22 +0800 | [diff] [blame] | 442 | end |