| Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame^] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2019 Intel Corp. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | */ |
| 15 | |
| 16 | /* |
| 17 | * This file is created based on Intel Tiger Lake Processor PCH Datasheet |
| 18 | * Document number: 575857 |
| 19 | * Chapter number: 4 |
| 20 | */ |
| 21 | |
| 22 | #include <bootstate.h> |
| 23 | #include <console/console.h> |
| 24 | #include <device/mmio.h> |
| 25 | #include <device/device.h> |
| 26 | #include <intelblocks/pmc.h> |
| 27 | #include <intelblocks/pmclib.h> |
| 28 | #include <intelblocks/rtc.h> |
| 29 | #include <soc/pci_devs.h> |
| 30 | #include <soc/pm.h> |
| 31 | #include <soc/soc_chip.h> |
| 32 | |
| 33 | /* |
| 34 | * Set which power state system will be after reapplying |
| 35 | * the power (from G3 State) |
| 36 | */ |
| 37 | void pmc_soc_set_afterg3_en(const bool on) |
| 38 | { |
| 39 | uint8_t reg8; |
| 40 | uint8_t *const pmcbase = pmc_mmio_regs(); |
| 41 | |
| 42 | reg8 = read8(pmcbase + GEN_PMCON_A); |
| 43 | if (on) |
| 44 | reg8 &= ~SLEEP_AFTER_POWER_FAIL; |
| 45 | else |
| 46 | reg8 |= SLEEP_AFTER_POWER_FAIL; |
| 47 | write8(pmcbase + GEN_PMCON_A, reg8); |
| 48 | } |
| 49 | |
| 50 | static void config_deep_sX(uint32_t offset, uint32_t mask, int sx, int enable) |
| 51 | { |
| 52 | uint32_t reg; |
| 53 | uint8_t *pmcbase = pmc_mmio_regs(); |
| 54 | |
| 55 | printk(BIOS_DEBUG, "%sabling Deep S%c\n", |
| 56 | enable ? "En" : "Dis", sx + '0'); |
| 57 | reg = read32(pmcbase + offset); |
| 58 | if (enable) |
| 59 | reg |= mask; |
| 60 | else |
| 61 | reg &= ~mask; |
| 62 | write32(pmcbase + offset, reg); |
| 63 | } |
| 64 | |
| 65 | static void config_deep_s5(int on_ac, int on_dc) |
| 66 | { |
| 67 | /* Treat S4 the same as S5. */ |
| 68 | config_deep_sX(S4_PWRGATE_POL, S4AC_GATE_SUS, 4, on_ac); |
| 69 | config_deep_sX(S4_PWRGATE_POL, S4DC_GATE_SUS, 4, on_dc); |
| 70 | config_deep_sX(S5_PWRGATE_POL, S5AC_GATE_SUS, 5, on_ac); |
| 71 | config_deep_sX(S5_PWRGATE_POL, S5DC_GATE_SUS, 5, on_dc); |
| 72 | } |
| 73 | |
| 74 | static void config_deep_s3(int on_ac, int on_dc) |
| 75 | { |
| 76 | config_deep_sX(S3_PWRGATE_POL, S3AC_GATE_SUS, 3, on_ac); |
| 77 | config_deep_sX(S3_PWRGATE_POL, S3DC_GATE_SUS, 3, on_dc); |
| 78 | } |
| 79 | |
| 80 | static void config_deep_sx(uint32_t deepsx_config) |
| 81 | { |
| 82 | uint32_t reg; |
| 83 | uint8_t *pmcbase = pmc_mmio_regs(); |
| 84 | |
| 85 | reg = read32(pmcbase + DSX_CFG); |
| 86 | reg &= ~DSX_CFG_MASK; |
| 87 | reg |= deepsx_config; |
| 88 | write32(pmcbase + DSX_CFG, reg); |
| 89 | } |
| 90 | |
| 91 | static void pmc_init(void *unused) |
| 92 | { |
| 93 | const config_t *config = config_of_soc(); |
| 94 | |
| 95 | rtc_init(); |
| 96 | |
| 97 | pmc_set_power_failure_state(true); |
| 98 | pmc_gpe_init(); |
| 99 | |
| 100 | pmc_set_acpi_mode(); |
| 101 | |
| 102 | config_deep_s3(config->deep_s3_enable_ac, config->deep_s3_enable_dc); |
| 103 | config_deep_s5(config->deep_s5_enable_ac, config->deep_s5_enable_dc); |
| 104 | config_deep_sx(config->deep_sx_config); |
| 105 | } |
| 106 | |
| 107 | /* |
| 108 | * Initialize PMC controller. |
| 109 | * |
| 110 | * PMC controller gets hidden from PCI bus during FSP-Silicon init call. |
| 111 | * Hence PCI enumeration can't be used to initialize bus device and |
| 112 | * allocate resources. |
| 113 | */ |
| 114 | BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_EXIT, pmc_init, NULL); |