Elyes HAOUAS | c4b7027 | 2020-05-13 11:42:12 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
Bora Guvendik | 3a1a037 | 2020-03-09 18:20:07 -0700 | [diff] [blame] | 2 | |
Furquan Shaikh | 76cedd2 | 2020-05-02 10:24:23 -0700 | [diff] [blame] | 3 | #include <acpi/acpi.h> |
Bora Guvendik | 3a1a037 | 2020-03-09 18:20:07 -0700 | [diff] [blame] | 4 | #include <baseboard/variants.h> |
Tim Wawrzynczak | d8bff38 | 2020-03-19 12:19:38 -0600 | [diff] [blame] | 5 | #include <baseboard/gpio.h> |
| 6 | #include <soc/gpio.h> |
| 7 | #include <variant/gpio.h> |
Kyösti Mälkki | 91c077f | 2021-11-03 18:34:14 +0200 | [diff] [blame^] | 8 | #include <vendorcode/google/chromeos/chromeos.h> |
Bora Guvendik | 3a1a037 | 2020-03-09 18:20:07 -0700 | [diff] [blame] | 9 | |
Bora Guvendik | 3a1a037 | 2020-03-09 18:20:07 -0700 | [diff] [blame] | 10 | static const struct pad_config gpio_table[] = { |
Tim Wawrzynczak | d8bff38 | 2020-03-19 12:19:38 -0600 | [diff] [blame] | 11 | /* A0 thru A6 are ESPI, configured elsewhere */ |
| 12 | /* A0 : ESPI_IO0 ==> ESPI_IO_0 */ |
| 13 | /* A1 : ESPI_IO1 ==> ESPI_IO_1 */ |
| 14 | /* A2 : ESPI_IO2 ==> ESPI_IO_2 */ |
| 15 | /* A3 : ESPI_IO3 ==> ESPI_IO_3 */ |
| 16 | /* A4 : ESPI_CS# ==> ESPI_CS_L */ |
| 17 | /* A5 : ESPI_CLK ==> ESPI_CLK */ |
| 18 | /* A6 : ESPI_RESET# ==> NC(TP764) */ |
| 19 | /* A7 : GPP_A7 ==> CNVI_EN# */ |
| 20 | PAD_CFG_GPI(GPP_A7, NONE, DEEP), |
| 21 | /* A8 : GPP_A8 ==> CNV_RF_RESET# */ |
| 22 | PAD_CFG_NF(GPP_A8, NONE, DEEP, NF2), |
| 23 | /* A9 : GPP_A9 ==> CLKREQ_CNV#_1P8 */ |
| 24 | PAD_CFG_NF(GPP_A9, NONE, DEEP, NF2), |
| 25 | /* A10 : GPP_A10 ==> TOUCH_SCREEN_RST# */ |
| 26 | PAD_CFG_GPO(GPP_A10, 0, DEEP), |
| 27 | /* A11 : GPP_A11 ==> NC */ |
| 28 | PAD_NC(GPP_A11, NONE), |
| 29 | /* A12 : GPP_A12 ==> M2280_PCIE_SATA# */ |
| 30 | PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), |
| 31 | /* A13 : GPP_A13 ==> PCH_BT_RADIO_DIS# */ |
Eric Lai | 5874c78 | 2020-04-29 14:23:21 +0800 | [diff] [blame] | 32 | PAD_CFG_GPO(GPP_A13, 1, DEEP), |
Tim Wawrzynczak | d8bff38 | 2020-03-19 12:19:38 -0600 | [diff] [blame] | 33 | /* A14 : GPP_A14 ==> USB_OC1# */ |
| 34 | PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), |
| 35 | /* A15 : GPP_A15 ==> USB_OC2# */ |
| 36 | PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), |
| 37 | /* A16 : GPP_A16 ==> USB_OC3# */ |
| 38 | PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), |
| 39 | /* A17 : GPP_A17 ==> NC */ |
| 40 | PAD_NC(GPP_A17, NONE), |
| 41 | /* A18 : GPP_A18 ==> HDMI_HPD */ |
| 42 | PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), |
| 43 | /* A19 : GPP_A19 ==> NC */ |
| 44 | PAD_NC(GPP_A19, NONE), |
| 45 | /* A20 : GPP_A20 ==> NC */ |
| 46 | PAD_NC(GPP_A20, NONE), |
| 47 | /* A21 : GPP_A21 ==> 3.3V_CAM_EN# */ |
| 48 | PAD_CFG_GPO(GPP_A21, 0, PLTRST), |
| 49 | /* A22 : GPP_A22 ==> KB_DET# */ |
| 50 | PAD_CFG_GPI(GPP_A22, NONE, PLTRST), |
| 51 | /* A23 : GPP_A23 ==> RECOVERY# */ |
| 52 | PAD_CFG_GPI(GPP_A23, NONE, DEEP), |
Bora Guvendik | 3a1a037 | 2020-03-09 18:20:07 -0700 | [diff] [blame] | 53 | |
Tim Wawrzynczak | d8bff38 | 2020-03-19 12:19:38 -0600 | [diff] [blame] | 54 | /* B0 : GPP_B0 ==> CORE_VID0 */ |
| 55 | PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), |
| 56 | /* B1 : GPP_B1 ==> CORE_VID1 */ |
| 57 | PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), |
| 58 | /* B2 : GPP_B2 ==> VRALERT_L */ |
| 59 | PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1), |
| 60 | /* B3 : GPP_B3 ==> TOUCH_SCREEN_PD# */ |
| 61 | PAD_CFG_GPO(GPP_B3, 0, PLTRST), |
| 62 | /* B4 : GPP_B4 ==> TOUCH_SCREEN_DET# */ |
| 63 | PAD_CFG_GPI(GPP_B4, NONE, DEEP), |
| 64 | /* B5 : GPP_B5 ==> ISH_I2C0_SDA */ |
| 65 | PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), |
| 66 | /* B6 : GPP_B6 ==> ISH_I2C0_SCL */ |
| 67 | PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), |
| 68 | /* B7 : GPP_B7 ==> NC */ |
| 69 | PAD_NC(GPP_B7, NONE), |
| 70 | /* B8 : GPP_B8 ==> NC */ |
| 71 | PAD_NC(GPP_B8, NONE), |
| 72 | /* B9 : GPP_B9 ==> NC */ |
| 73 | PAD_NC(GPP_B9, NONE), |
| 74 | /* B10 : GPP_B10 ===> NC */ |
| 75 | PAD_NC(GPP_B10, NONE), |
| 76 | /* B11 : GPP_B11 ==> TBT_I2C_INT# */ |
Anil Kumar | 7ac6a98 | 2020-05-13 13:07:26 -0700 | [diff] [blame] | 77 | PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), |
Tim Wawrzynczak | d8bff38 | 2020-03-19 12:19:38 -0600 | [diff] [blame] | 78 | /* B12 : GPP_B12 ==> SIO_SLP_S0# */ |
| 79 | PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), |
| 80 | /* B13 : PLTRST# ==> PCH_PLTRST# */ |
| 81 | PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), |
| 82 | /* B14 : GPP_B14 ==> SPKR (PIN STRAP, Top Swap Override) */ |
| 83 | PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), |
| 84 | /* B15 : GPP_B15 ==> SPK_DET0# */ |
| 85 | PAD_CFG_GPI(GPP_B15, NONE, PLTRST), |
| 86 | /* B16 : GPP_B16 ==> ONE_DIMM# */ |
| 87 | PAD_CFG_GPI(GPP_B16, NONE, PLTRST), |
| 88 | /* B17 : GPP_B17 ==> HOST_SD_WP# */ |
| 89 | PAD_CFG_GPO(GPP_B17, 0, PLTRST), |
| 90 | /* B18 : GPP_B18 ==> NRB_BIT (PIN STRAP, No Reboot) */ |
| 91 | PAD_NC(GPP_B18, NONE), |
| 92 | /* B19 : GPP_B19 ==> D3_RST# */ |
| 93 | PAD_CFG_GPO(GPP_B19, 0, DEEP), |
| 94 | /* B20 : GPP_B20 ==> LCD_CBL_DET# */ |
| 95 | PAD_CFG_GPI(GPP_B20, NONE, PLTRST), |
| 96 | /* B21 : GPP_B21 ==> PCH_TOUCH_SCREEN_EN */ |
| 97 | PAD_CFG_GPO(GPP_B21, 0, DEEP), |
| 98 | /* B22 : GPP_B22 ==> NC */ |
| 99 | PAD_NC(GPP_B22, NONE), |
| 100 | /* B23 : GPP_B23 ==> NC (PIN STRAP, CPUNSSC frequency) */ |
| 101 | PAD_NC(GPP_B23, NONE), |
Bora Guvendik | 3a1a037 | 2020-03-09 18:20:07 -0700 | [diff] [blame] | 102 | |
Tim Wawrzynczak | d8bff38 | 2020-03-19 12:19:38 -0600 | [diff] [blame] | 103 | /* C0 : GPP_C0 ==> MEM_SMBCLK */ |
| 104 | PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), |
| 105 | /* C1 : GPP_C1 ==> MEM_SMBDATA */ |
| 106 | PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), |
| 107 | /* C2 : GPP_C2 ==> NC (PIN STRAP, TLS Confidentiality) */ |
| 108 | PAD_NC(GPP_C2, NONE), |
| 109 | /* C3 : GPP_C3 ==> SML0_SMBCLK */ |
| 110 | PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), |
| 111 | /* C4 : GPP_C4 ==> SML0_SMBDATA */ |
| 112 | PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), |
| 113 | /* C5 : GPP_C5 ==> NC (PIN STRAP, Boot Strap 0) */ |
| 114 | PAD_NC(GPP_C5, NONE), |
| 115 | /* C6 : GPP_C6 ==> SML1_SMBCLK */ |
| 116 | PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), |
| 117 | /* C7 : GPP_C7 ==> SML1_SMBDATA */ |
| 118 | PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), |
| 119 | /* C8 : GPP_C8 ==> WWAN_FULL_POWER_EN */ |
| 120 | PAD_CFG_GPO(GPP_C8, 1, DEEP), |
| 121 | /* C9 : GPP_C9 ==> SBIOS_TX */ |
| 122 | PAD_CFG_GPO(GPP_C9, 0, PLTRST), |
| 123 | /* C10 : GPP_C10 ==> NC */ |
| 124 | PAD_NC(GPP_C10, NONE), |
| 125 | /* C11 : GPP_C11 ==> NC */ |
| 126 | PAD_NC(GPP_C11, NONE), |
| 127 | /* C12 : GPP_C12 ==> NC */ |
| 128 | PAD_NC(GPP_C12, NONE), |
| 129 | /* C13 : GPP_C13 ==> PCH_SSD_PWR_EN */ |
| 130 | PAD_CFG_GPO(GPP_C13, 1, DEEP), |
| 131 | /* C14 : GPP_C14 ==> NC */ |
| 132 | PAD_NC(GPP_C14, NONE), |
| 133 | /* C15 : GPP_C15 ==> NC */ |
| 134 | PAD_NC(GPP_C15, NONE), |
| 135 | /* C16 : GPP_C16 ==> I2C0_SDA_TS */ |
| 136 | PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), |
| 137 | /* C17 : GPP_C17 ==> I2C0_SCL_TS */ |
| 138 | PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), |
| 139 | /* C18 : GPP_C18 ==> I2C1_SDA_TP */ |
| 140 | PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), |
| 141 | /* C19 : GPP_C19 ==> I2C1_SCL_TP */ |
| 142 | PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), |
| 143 | /* C20 : GPP_C20 ==> PCHRX_SERVOTX_UART */ |
| 144 | PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), |
| 145 | /* C21 : CPP_G21 ==> PCHTX_SERVORX_UART */ |
| 146 | PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), |
| 147 | /* C22 : GPP_C22 ==> H1_FLASH_WP */ |
| 148 | PAD_CFG_GPI(GPP_C22, NONE, DEEP), |
| 149 | /* C23 : GPP_C23 ==> H1_PCH_INT# */ |
| 150 | PAD_CFG_GPI_APIC(GPP_C23, NONE, DEEP, LEVEL, INVERT), |
Bora Guvendik | 3a1a037 | 2020-03-09 18:20:07 -0700 | [diff] [blame] | 151 | |
Tim Wawrzynczak | d8bff38 | 2020-03-19 12:19:38 -0600 | [diff] [blame] | 152 | /* D0 : GPP_D0 ==> ISH_ACC1_INT */ |
| 153 | PAD_CFG_NF(GPP_D0, NONE, DEEP, NF1), |
| 154 | /* D1 : GPP_D1 ==> ISH_ACC2_INT */ |
| 155 | PAD_CFG_NF(GPP_D1, NONE, DEEP, NF1), |
| 156 | /* D2 : GPP_D2 ==> ISH_TABLE_MODE# */ |
| 157 | PAD_CFG_NF(GPP_D2, NONE, DEEP, NF1), |
| 158 | /* D3 : GPP_D3 ==> ISH_ALS_INT# */ |
| 159 | PAD_CFG_NF(GPP_D3, NONE, DEEP, NF1), |
| 160 | /* D4 : GPP_D4 ==> RT_FORCE_PWR */ |
| 161 | PAD_CFG_GPO(GPP_D4, 0, PLTRST), |
| 162 | /* D5 : GPP_D5 ==> CLKREQ_PCIE#0 */ |
| 163 | PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), |
| 164 | /* D6 : GPP_D6 ==> CLKREQ_PCIE#1 */ |
| 165 | PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), |
| 166 | /* D7 : GPP_D7 ==> CLKREQ_PCIE#2 */ |
| 167 | PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), |
| 168 | /* D8 : GPP_D8 ==> CLKREQ_PCIE#3 */ |
| 169 | PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), |
| 170 | /* D9 : GPP_D9 ==> TBT_2_LSX_TX */ |
| 171 | PAD_CFG_NF(GPP_D9, NONE, DEEP, NF4), |
| 172 | /* D10 : GPP_D10 ==> TBT_2_LSX_RX */ |
| 173 | PAD_CFG_NF(GPP_D10, NONE, DEEP, NF4), |
| 174 | /* D11 : GPP_D11 ==> TBT_3_LSX_TX */ |
| 175 | PAD_CFG_NF(GPP_D11, NONE, DEEP, NF4), |
| 176 | /* D12 : GPP_D12 ==> TBT_3_LSX_RX */ |
| 177 | PAD_CFG_NF(GPP_D12, DN_20K, DEEP, NF4), |
| 178 | /* D13 : GPP_D13 ==> SML0B_SMLDATA */ |
| 179 | PAD_CFG_NF(GPP_D13, NONE, DEEP, NF2), |
| 180 | /* D14 : GPP_D14 ==> SML0B_SMLCLK */ |
| 181 | PAD_CFG_NF(GPP_D14, NONE, DEEP, NF2), |
| 182 | /* D15 : GPP_D15 ==> NC */ |
| 183 | PAD_NC(GPP_D15, NONE), |
| 184 | /* D16 : GPP_D16 ==> SML0BALERT# */ |
| 185 | PAD_CFG_NF(GPP_D16, NONE, DEEP, NF2), |
| 186 | /* D17 : GPP_D17 ==> ISH_NB_MODE# */ |
| 187 | PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), |
| 188 | /* D18 : GPP_D18 ==> ISH_LID_CL#_NB */ |
| 189 | PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), |
| 190 | /* D19 : GPP_D19 ==> NC */ |
| 191 | PAD_NC(GPP_D19, NONE), |
| 192 | |
| 193 | /* E0 : GPP_E0 ==> NC */ |
| 194 | PAD_NC(GPP_E0, NONE), |
| 195 | /* E1 : GPP_E1 ==> TOUCH_SCREEN_INT# */ |
| 196 | PAD_CFG_GPI_APIC(GPP_E1, NONE, PLTRST, LEVEL, INVERT), |
| 197 | /* E2 : GPP_E2 ==> MEDIACARD_IRQ# */ |
| 198 | PAD_CFG_GPI_APIC(GPP_E2, NONE, PLTRST, LEVEL, INVERT), |
| 199 | /* E3 : GPP_E3 ==> MEM_INTERLEAVED */ |
| 200 | PAD_CFG_GPI(GPP_E3, NONE, PLTRST), |
| 201 | /* E4 : GPP_E4 ==> NC */ |
| 202 | PAD_NC(GPP_E4, NONE), |
| 203 | /* E5 : GPP_E5 ==> M2280_DEVSLP */ |
| 204 | PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), |
| 205 | /* E6 : GPP_E6 ==> (PIN STRAP, Reserved) */ |
| 206 | PAD_NC(GPP_E6, NONE), |
| 207 | /* E7 : CPU_GP1 ==> PCH_TOUCHPAD_INTR# */ |
| 208 | PAD_CFG_GPI_IRQ_WAKE(GPP_E7, NONE, PLTRST, LEVEL, INVERT), |
| 209 | /* E8 : GPP_E8 ==> SECURE_BIO */ |
| 210 | PAD_CFG_GPO(GPP_E8, 0, PLTRST), |
| 211 | /* E9 : GPP_E9 ==> OC0# */ |
| 212 | PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), |
| 213 | /* E10 : GPP_E10 ==> HDMI_PD# */ |
| 214 | PAD_CFG_GPO(GPP_E10, 1, DEEP), |
| 215 | /* E11 : GPP_E11 ==> VPRO_DET# */ |
| 216 | PAD_CFG_GPI(GPP_E11, NONE, PLTRST), |
| 217 | /* E12 : GPP_E12 ==> RTC_DET# */ |
| 218 | PAD_CFG_GPI(GPP_E12, NONE, PLTRST), |
| 219 | /* E13 : GPP_E13 ==> TBT_DET# */ |
| 220 | PAD_CFG_GPI(GPP_E13, NONE, DEEP), |
| 221 | /* E14 : GPP_E14 ==> EPD_HPD */ |
| 222 | PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), |
| 223 | /* E15 : GPP_E15 ==> ISH_LID_CL#_TAB */ |
| 224 | PAD_CFG_NF(GPP_E15, NONE, DEEP, NF1), |
| 225 | /* E16 : GPP_E16 ==> NC */ |
| 226 | PAD_NC(GPP_E16, NONE), |
| 227 | /* E17 : GPP_E17 ==> NC */ |
| 228 | PAD_NC(GPP_E17, NONE), |
| 229 | /* E18 : GPP_E18 ==> TBT_LSX0_TXD */ |
| 230 | PAD_CFG_NF(GPP_E18, NONE, DEEP, NF4), |
| 231 | /* E19 : GPP_E19 ==> TBT_LSX0_RXD */ |
| 232 | PAD_CFG_NF(GPP_E19, NONE, DEEP, NF4), |
| 233 | /* E20 : GPP_E20 ==> TBT_LSX1_TXD */ |
| 234 | PAD_CFG_NF(GPP_E20, NONE, DEEP, NF4), |
| 235 | /* E21 : GPP_E21 ==> TBT_LSX1_RXD */ |
| 236 | PAD_CFG_NF(GPP_E21, NONE, DEEP, NF4), |
| 237 | /* E22 : GPP_E22 ==> NC */ |
| 238 | PAD_NC(GPP_E22, NONE), |
| 239 | /* E23 : GPP_E23 ==> NC */ |
| 240 | PAD_NC(GPP_E23, NONE), |
| 241 | |
| 242 | /* F0 : GPP_F0 ==> BRI_DT_1P8 */ |
| 243 | PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), |
| 244 | /* F1 : GPP_F1 ==> CNV_BRI_RSP_1P8 */ |
| 245 | PAD_CFG_NF(GPP_F1, NONE, DEEP, NF1), |
| 246 | /* F2 : GPP_F2 ==> CNV_RGI_DT_1P8 */ |
| 247 | PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), |
| 248 | /* F3 : GPP_F3 ==> CNV_RGI_RSP_1P8 */ |
| 249 | PAD_CFG_NF(GPP_F3, NONE, DEEP, NF1), |
| 250 | /* F4 : GPP_F4 ==> NC */ |
| 251 | PAD_NC(GPP_F4, NONE), |
| 252 | /* F5 : GPP_F5 ==> NC */ |
| 253 | PAD_NC(GPP_F5, NONE), |
| 254 | /* F6 : GPP_F6 ==> NC */ |
| 255 | PAD_NC(GPP_F6, NONE), |
| 256 | /* F7 : GPP_F7 ==> NC (PIN STRAP, Reserved) */ |
| 257 | PAD_NC(GPP_F7, NONE), |
| 258 | /* F8 : GPP_F8 ==> NC */ |
| 259 | PAD_NC(GPP_F8, NONE), |
| 260 | /* F9 : GPP_F9 ==> NC */ |
| 261 | PAD_NC(GPP_F9, NONE), |
| 262 | /* F10 : GPP_F10 ==> NC (PIN STRAP, Reserved) */ |
| 263 | PAD_NC(GPP_F10, NONE), |
| 264 | /* F11 : GPP_F11 ==> MEM_CONFIG0_1P8 */ |
| 265 | PAD_CFG_GPI(GPP_F11, NONE, DEEP), |
| 266 | /* F12 : GPP_F12 ==> MEM_CONFIG1_1P8 */ |
| 267 | PAD_CFG_GPI(GPP_F12, NONE, DEEP), |
| 268 | /* F13 : GPP_F13 ==> MEM_CONFIG2_1P8 */ |
| 269 | PAD_CFG_GPI(GPP_F13, NONE, DEEP), |
| 270 | /* F14 : GPP_F14 ==> MEM_CONFIG3_1P8 */ |
| 271 | PAD_CFG_GPI(GPP_F14, NONE, DEEP), |
| 272 | /* F15 : GPP_F15 ==> MEM_CONFIG4_1P8 */ |
| 273 | PAD_CFG_GPI(GPP_F15, NONE, DEEP), |
| 274 | /* F16 : GPP_F16 ==> WWAN_BB_RST#_1P8 */ |
| 275 | PAD_CFG_GPO(GPP_F16, 1, DEEP), |
| 276 | /* F17 : GPP_F17 ==> WWAN_GPIO_PERST# */ |
| 277 | PAD_CFG_GPO(GPP_F17, 0, DEEP), |
| 278 | /* F18 : GPP_F18 ==> WWAN_GPIO_WAKE# */ |
| 279 | PAD_CFG_GPI_SCI_LOW(GPP_F18, NONE, DEEP, EDGE_SINGLE), |
| 280 | /* F19 : GPP_F19 ==> CAM_MIC_CBL_DET# */ |
| 281 | PAD_CFG_GPI(GPP_F19, NONE, PLTRST), |
| 282 | /* F20 : GPP_F20 ==> NC */ |
| 283 | PAD_NC(GPP_F20, NONE), |
| 284 | /* F21 : GPP_F21 ==> NC */ |
| 285 | PAD_NC(GPP_F21, NONE), |
| 286 | /* F22 : VNN_CTRL */ |
| 287 | PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), |
| 288 | /* F23 : V1P05_CTRL */ |
| 289 | PAD_CFG_NF(GPP_F23, NONE, DEEP, NF1), |
| 290 | |
| 291 | /* H0 : GPPH0_BOOT_STRAP1 */ |
| 292 | PAD_NC(GPP_H0, NONE), |
| 293 | /* H1 : GPPH1_BOOT_STRAP2 */ |
| 294 | PAD_NC(GPP_H1, NONE), |
| 295 | /* H2 : GPPH2_BOOT_STRAP3 */ |
| 296 | PAD_NC(GPP_H2, NONE), |
| 297 | /* H3 : GPP_H3 ==> NC */ |
| 298 | PAD_NC(GPP_H3, NONE), |
| 299 | /* H4 : GPP_H4 ==> DDR_CHA_EN_1P8 */ |
| 300 | PAD_CFG_GPI(GPP_H4, NONE, DEEP), |
| 301 | /* H5 : GPP_H5 ==> DDR_CHB_EN_1P8 */ |
| 302 | PAD_CFG_GPI(GPP_H5, NONE, DEEP), |
Eric Lai | a48e711 | 2020-04-17 19:32:33 +0800 | [diff] [blame] | 303 | /* H6 : GPP_H6 ==> I2C_SDA_PCH_H1 */ |
| 304 | PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), |
| 305 | /* H7 : GPP_H7 ==> I2C_SCL_PCH_H1 */ |
| 306 | PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), |
| 307 | /* H8 : GPP_H8 ==> NC */ |
| 308 | PAD_NC(GPP_H8, NONE), |
| 309 | /* H9 : GPP_H9 ==> NC */ |
| 310 | PAD_NC(GPP_H9, NONE), |
Tim Wawrzynczak | d8bff38 | 2020-03-19 12:19:38 -0600 | [diff] [blame] | 311 | /* H10 : GPP_H10 ==> CLKREQ_PCIE#4 */ |
| 312 | PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), |
| 313 | /* H11 : GPP_H11 ==> CLKREQ_PCIE#5 */ |
| 314 | PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), |
| 315 | /* H12 : GPP_H12 ==> NC */ |
| 316 | PAD_NC(GPP_H12, NONE), |
| 317 | /* H13 : GPP_H13 ==> NC */ |
| 318 | PAD_NC(GPP_H13, NONE), |
| 319 | /* H14 : GPP_H14 ==> NC */ |
| 320 | PAD_NC(GPP_H14, NONE), |
| 321 | /* H15 : GPP_H15 ==> NC */ |
| 322 | PAD_NC(GPP_H15, NONE), |
| 323 | /* H16 : GPP_H16 ==> CPU_DPB_CTRL_CLK */ |
| 324 | PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1), |
| 325 | /* H17 : GPP_H17 ==> CPU_DPB_CTRL_DATA */ |
| 326 | PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), |
| 327 | /* H18 : CPU_C10_GATE# ==> CPU_C10_GATE# */ |
| 328 | PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), |
| 329 | /* H19 : GPP_H19 ==> NC */ |
| 330 | PAD_NC(GPP_H19, NONE), |
| 331 | /* H20 : GPP_H20 ==> NC */ |
| 332 | PAD_NC(GPP_H20, NONE), |
| 333 | /* H21 : GPP_H21 ==> NC */ |
| 334 | PAD_NC(GPP_H21, NONE), |
| 335 | /* H22 : GPP_H22 ==> NC */ |
| 336 | PAD_NC(GPP_H22, NONE), |
| 337 | /* H23 : GPP_H23 ==> NC */ |
| 338 | PAD_NC(GPP_H23, NONE), |
| 339 | |
| 340 | /* R0 : GPP_R0 ==> HDA_BCLK */ |
| 341 | PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), |
| 342 | /* R1 : GPP_R1 ==> HDA_SYNC */ |
| 343 | PAD_CFG_NF(GPP_R1, NONE, DEEP, NF1), |
| 344 | /* R2 : GPP_R2 ==> HDA_SDO (PIN STRAP, Flash Descriptor Security Override */ |
| 345 | PAD_CFG_NF(GPP_R2, NONE, DEEP, NF1), |
| 346 | /* R3 : GPP_R3 ==> HDA_SDIO */ |
| 347 | PAD_CFG_NF(GPP_R3, NONE, DEEP, NF1), |
| 348 | /* R4 : GPP_R4 ==> HDA_RST# */ |
| 349 | PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1), |
| 350 | /* R5 : GPP_R5 ==> NC */ |
| 351 | PAD_NC(GPP_R5, NONE), |
| 352 | /* R6 : GPP_R6 ==> SD_PWR_EN1 */ |
| 353 | PAD_CFG_GPO(GPP_R6, 0, PLTRST), |
| 354 | /* R7 : GPP_R7 ==> SD_PWR_EN2 */ |
| 355 | PAD_CFG_GPO(GPP_R7, 0, PLTRST), |
| 356 | |
| 357 | /* S0 : GPP_S0 ==> NC */ |
| 358 | PAD_NC(GPP_S0, NONE), |
| 359 | /* S1 : GPP_S1 ==> NC */ |
| 360 | PAD_NC(GPP_S1, NONE), |
| 361 | /* S2 : GPP_S2 ==> NC */ |
| 362 | PAD_NC(GPP_S2, NONE), |
| 363 | /* S3 : GPP_S3 ==> NC */ |
| 364 | PAD_NC(GPP_S3, NONE), |
| 365 | /* S4 : GPP_S4 ==> NC */ |
| 366 | PAD_NC(GPP_S4, NONE), |
| 367 | /* S5 : GPP_S5 ==> NC */ |
| 368 | PAD_NC(GPP_S5, NONE), |
| 369 | /* S6 : GPP_S6 ==> NC */ |
| 370 | PAD_NC(GPP_S6, NONE), |
| 371 | /* S7 : GPP_S7 ==> NC */ |
| 372 | PAD_NC(GPP_S7, NONE), |
| 373 | |
| 374 | /* GPD0: GPD0 ==> PCH_BATLOW# */ |
| 375 | PAD_CFG_NF(GPD0, NONE, DEEP, NF1), |
| 376 | /* GPD1: GPD1 ==> AC_PRESENT */ |
| 377 | PAD_CFG_NF(GPD1, NONE, DEEP, NF1), |
| 378 | /* GPD2: GPD2 ==> LAN_WAKE# */ |
| 379 | PAD_CFG_NF(GPD2, NONE, DEEP, NF1), |
| 380 | /* GPD3: GPD3 ==> SIO_PWRBTN# */ |
| 381 | PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), |
| 382 | /* GPD4: GPD4 ==> SIO_SLP_S3# */ |
| 383 | PAD_CFG_NF(GPD4, NONE, DEEP, NF1), |
| 384 | /* GPD5: GPD5 ==> SIO_SLP_S4# */ |
| 385 | PAD_CFG_NF(GPD5, NONE, DEEP, NF1), |
| 386 | /* GPD6: GPD6 ==> SIO_SLP_A# */ |
| 387 | PAD_CFG_NF(GPD6, NONE, DEEP, NF1), |
| 388 | /* GPD7: GPD7 ==> PCH_TBT_PERST# (PIN STRAP, Reserved) */ |
| 389 | PAD_CFG_GPO(GPD7, 0, PLTRST), |
| 390 | /* GPD8: GPD8 ==> SUSCLK */ |
| 391 | PAD_CFG_NF(GPD8, NONE, DEEP, NF1), |
| 392 | /* GPD9: GPD9 ==> SIO_SLP_WLAN# */ |
| 393 | PAD_CFG_NF(GPD9, NONE, DEEP, NF1), |
| 394 | /* GPD10: GPD10 ==> SIO_SLP_S5# */ |
| 395 | PAD_CFG_NF(GPD10, NONE, DEEP, NF1), |
| 396 | /* GPD11: GPD11 ==> PM_LANPHY_EN */ |
| 397 | PAD_CFG_NF(GPD11, NONE, DEEP, NF1), |
Bora Guvendik | 3a1a037 | 2020-03-09 18:20:07 -0700 | [diff] [blame] | 398 | }; |
| 399 | |
| 400 | const struct pad_config *__weak variant_base_gpio_table(size_t *num) |
| 401 | { |
| 402 | *num = ARRAY_SIZE(gpio_table); |
| 403 | return gpio_table; |
| 404 | } |
| 405 | |
Bora Guvendik | 3a1a037 | 2020-03-09 18:20:07 -0700 | [diff] [blame] | 406 | static const struct cros_gpio cros_gpios[] = { |
Shaunak Saha | 56e3df4 | 2020-03-24 00:24:59 -0700 | [diff] [blame] | 407 | CROS_GPIO_REC_AL(GPIO_REC_MODE, CROS_GPIO_DEVICE_NAME), |
| 408 | CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME), |
Bora Guvendik | 3a1a037 | 2020-03-09 18:20:07 -0700 | [diff] [blame] | 409 | }; |
| 410 | |
| 411 | const struct cros_gpio *__weak variant_cros_gpios(size_t *num) |
| 412 | { |
| 413 | *num = ARRAY_SIZE(cros_gpios); |
| 414 | return cros_gpios; |
| 415 | } |
Tim Wawrzynczak | d8bff38 | 2020-03-19 12:19:38 -0600 | [diff] [blame] | 416 | |
| 417 | /* Weak implementation of overrides */ |
| 418 | const struct pad_config *__weak variant_override_gpio_table(size_t *num) |
| 419 | { |
| 420 | *num = 0; |
| 421 | return NULL; |
| 422 | } |
| 423 | |
| 424 | /* Weak implementation of early gpio */ |
| 425 | const struct pad_config *__weak variant_early_gpio_table(size_t *num) |
| 426 | { |
Eric Lai | 184b1ce | 2020-04-21 17:59:25 +0800 | [diff] [blame] | 427 | *num = 0; |
| 428 | return NULL; |
Tim Wawrzynczak | d8bff38 | 2020-03-19 12:19:38 -0600 | [diff] [blame] | 429 | } |
Anil Kumar | c6f5b05 | 2020-03-26 16:35:23 -0700 | [diff] [blame] | 430 | |
| 431 | int __weak has_360_sensor_board(void) |
| 432 | { |
| 433 | return 0; |
| 434 | } |