Wisley Chen | c049c80 | 2021-07-19 20:11:39 +0600 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
| 2 | |
| 3 | #include <baseboard/gpio.h> |
| 4 | #include <baseboard/variants.h> |
| 5 | #include <commonlib/helpers.h> |
| 6 | #include <soc/gpio.h> |
Wisley Chen | c049c80 | 2021-07-19 20:11:39 +0600 | [diff] [blame] | 7 | |
| 8 | /* Pad configuration in ramstage */ |
| 9 | static const struct pad_config override_gpio_table[] = { |
| 10 | /* A17 : DISP_MISCC ==> NC */ |
| 11 | PAD_NC(GPP_A17, NONE), |
| 12 | /* A19 : DDSP_HPD1 ==> NC */ |
| 13 | PAD_NC(GPP_A19, NONE), |
| 14 | /* A20 : DDSP_HPD2 ==> NC */ |
| 15 | PAD_NC(GPP_A20, NONE), |
| 16 | /* A21 : DDPC_CTRCLK ==> NC */ |
| 17 | PAD_NC(GPP_A21, NONE), |
| 18 | /* A22 : DDPC_CTRLDATA ==> NC */ |
| 19 | PAD_NC(GPP_A22, NONE), |
| 20 | |
| 21 | /* B3 : PROC_GP2 ==> NC */ |
| 22 | PAD_NC(GPP_B3, NONE), |
| 23 | /* B15 : TIME_SYNC0 ==> NC */ |
| 24 | PAD_NC(GPP_B15, NONE), |
| 25 | |
| 26 | /* C3 : SML0CLK ==> NC */ |
| 27 | PAD_NC(GPP_C3, NONE), |
| 28 | /* C4 : SML0DATA ==> NC */ |
| 29 | PAD_NC(GPP_C4, NONE), |
| 30 | |
| 31 | /* D7 : SRCCLKREQ2# ==> NC */ |
| 32 | PAD_NC(GPP_D7, NONE), |
| 33 | /* D13 : ISH_UART0_RXD ==> NC */ |
| 34 | PAD_NC(GPP_D13, NONE), |
| 35 | |
Wisley Chen | c049c80 | 2021-07-19 20:11:39 +0600 | [diff] [blame] | 36 | /* E3 : PROC_GP0 ==> NC */ |
| 37 | PAD_NC(GPP_E3, NONE), |
| 38 | /* E7 : PROC_GP1 ==> NC */ |
| 39 | PAD_NC(GPP_E7, NONE), |
| 40 | /* E20 : DDP2_CTRLCLK ==> NC */ |
| 41 | PAD_NC(GPP_E20, NONE), |
| 42 | /* E22 : DDPA_CTRLCLK ==> NC */ |
| 43 | PAD_NC(GPP_E22, NONE), |
| 44 | /* E23 : DDPA_CTRLDATA ==> NC */ |
| 45 | PAD_NC(GPP_E23, NONE), |
| 46 | |
| 47 | /* F20 : EXT_PWR_GATE# ==> NC */ |
| 48 | PAD_NC(GPP_F20, NONE), |
| 49 | |
| 50 | /* H3 : SX_EXIT_HOLDOFF# ==> NC */ |
| 51 | PAD_NC(GPP_H3, NONE), |
| 52 | /* H20 : IMGCLKOUT1 ==> NC */ |
| 53 | PAD_NC(GPP_H20, NONE), |
| 54 | /* H21 : IMGCLKOUT2 ==> Privacy screen */ |
| 55 | PAD_CFG_GPO(GPP_H21, 0, DEEP), |
| 56 | |
| 57 | /* R6 : I2S_PCH_TX_SPKR_RX ==> NC */ |
| 58 | PAD_NC(GPP_R6, NONE), |
| 59 | /* R7 : I2S_PCH_RX_SPKR_TX ==> NC */ |
| 60 | PAD_NC(GPP_R7, NONE), |
| 61 | |
| 62 | /* S4 : SNDW2_CLK ==> NC */ |
| 63 | PAD_NC(GPP_S4, NONE), |
| 64 | /* S5 : SNDW2_DATA ==> NC */ |
| 65 | PAD_NC(GPP_S5, NONE), |
| 66 | /* S6 : SNDW3_CLK ==> NC */ |
| 67 | PAD_NC(GPP_S6, NONE), |
| 68 | /* S7 : SNDW3_DATA ==> NC */ |
| 69 | PAD_NC(GPP_S7, NONE), |
| 70 | |
| 71 | }; |
| 72 | |
| 73 | /* Early pad configuration in bootblock */ |
| 74 | static const struct pad_config early_gpio_table[] = { |
| 75 | /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ |
| 76 | PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), |
| 77 | /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ |
| 78 | PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2), |
| 79 | /* B8 : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */ |
| 80 | PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2), |
| 81 | /* |
| 82 | * D1 : ISH_GP1 ==> FP_RST_ODL |
| 83 | * FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down. |
| 84 | * To ensure proper power sequencing for the FPMCU device, reset signal is driven low |
| 85 | * early on in bootblock, followed by enabling of power. Reset signal is deasserted |
| 86 | * later on in ramstage. Since reset signal is asserted in bootblock, it results in |
| 87 | * FPMCU not working after a S3 resume. This is a known issue. |
| 88 | */ |
| 89 | PAD_CFG_GPO(GPP_D1, 0, DEEP), |
| 90 | /* D2 : ISH_GP2 ==> EN_FP_PWR */ |
| 91 | PAD_CFG_GPO(GPP_D2, 1, DEEP), |
Wisley Chen | 04613e9 | 2021-09-13 10:08:03 +0600 | [diff] [blame] | 92 | /* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */ |
| 93 | PAD_CFG_GPO(GPP_D11, 1, DEEP), |
Wisley Chen | c049c80 | 2021-07-19 20:11:39 +0600 | [diff] [blame] | 94 | /* E0 : SATAXPCIE0 ==> NC */ |
| 95 | PAD_NC(GPP_E0, NONE), |
| 96 | /* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */ |
| 97 | PAD_CFG_GPI(GPP_E13, NONE, DEEP), |
| 98 | /* E15 : RSVD_TP ==> PCH_WP_OD */ |
| 99 | PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), |
| 100 | /* E16 : RSVD_TP ==> WWAN_RST_L */ |
| 101 | PAD_CFG_GPO(GPP_E16, 0, DEEP), |
Tim Wawrzynczak | 36721a4 | 2021-10-07 16:02:11 -0600 | [diff] [blame] | 102 | /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ |
| 103 | PAD_CFG_GPI(GPP_F18, NONE, DEEP), |
Wisley Chen | c049c80 | 2021-07-19 20:11:39 +0600 | [diff] [blame] | 104 | /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */ |
| 105 | PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), |
| 106 | /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ |
| 107 | PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), |
Wisley Chen | 04613e9 | 2021-09-13 10:08:03 +0600 | [diff] [blame] | 108 | /* |
| 109 | * enable EN_PP3300_SSD in bootblock, then PERST# is asserted, and |
| 110 | * then deassert PERST# in ramstage |
| 111 | */ |
Wisley Chen | c049c80 | 2021-07-19 20:11:39 +0600 | [diff] [blame] | 112 | /* H13 : I2C7_SCL ==> EN_PP3300_SD */ |
| 113 | PAD_CFG_GPO(GPP_H13, 1, DEEP), |
Wisley Chen | 04613e9 | 2021-09-13 10:08:03 +0600 | [diff] [blame] | 114 | /* B4 : PROC_GP3 ==> SSD_PERST_L */ |
| 115 | PAD_CFG_GPO(GPP_B4, 0, DEEP), |
Wisley Chen | c049c80 | 2021-07-19 20:11:39 +0600 | [diff] [blame] | 116 | }; |
| 117 | |
| 118 | const struct pad_config *variant_gpio_override_table(size_t *num) |
| 119 | { |
| 120 | *num = ARRAY_SIZE(override_gpio_table); |
| 121 | return override_gpio_table; |
| 122 | } |
| 123 | |
| 124 | const struct pad_config *variant_early_gpio_table(size_t *num) |
| 125 | { |
| 126 | *num = ARRAY_SIZE(early_gpio_table); |
| 127 | return early_gpio_table; |
| 128 | } |