David Wu | 93a6c39 | 2021-08-12 17:45:44 +0800 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
| 2 | |
| 3 | #include <baseboard/gpio.h> |
| 4 | #include <baseboard/variants.h> |
| 5 | #include <commonlib/helpers.h> |
| 6 | #include <soc/gpio.h> |
David Wu | 93a6c39 | 2021-08-12 17:45:44 +0800 | [diff] [blame] | 7 | |
| 8 | /* Pad configuration in ramstage */ |
| 9 | static const struct pad_config override_gpio_table[] = { |
| 10 | /* A6 : ESPI_ALERT1# ==> NC */ |
| 11 | PAD_NC(GPP_A6, NONE), |
| 12 | /* A7 : SRCCLK_OE7# ==> NC */ |
| 13 | PAD_NC(GPP_A7, NONE), |
| 14 | /* A8 : SRCCLKREQ7# ==> NC */ |
| 15 | PAD_NC(GPP_A8, NONE), |
| 16 | /* A12 : SATAXPCIE1 ==> NC */ |
| 17 | PAD_NC(GPP_A12, NONE), |
| 18 | /* A15 : USB_OC2# ==> NC */ |
| 19 | PAD_NC(GPP_A15, NONE), |
| 20 | /* A19 : DDSP_HPD1 ==> NC */ |
| 21 | PAD_NC(GPP_A19, NONE), |
| 22 | /* A20 : DDSP_HPD2 ==> NC */ |
| 23 | PAD_NC(GPP_A20, NONE), |
| 24 | /* A21 : DDPC_CTRCLK ==> NC */ |
| 25 | PAD_NC(GPP_A21, NONE), |
| 26 | /* A22 : DDPC_CTRLDATA ==> NC */ |
| 27 | PAD_NC(GPP_A22, NONE), |
| 28 | |
| 29 | /* D3 : ISH_GP3 ==> NC */ |
| 30 | PAD_NC(GPP_D3, NONE), |
David Wu | 7181cd2 | 2021-08-27 17:49:05 +0800 | [diff] [blame] | 31 | /* D5 : SRCCLKREQ0# ==> SSD_CLKREQ_ODL */ |
| 32 | PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), |
David Wu | 93a6c39 | 2021-08-12 17:45:44 +0800 | [diff] [blame] | 33 | /* D7 : SRCCLKREQ2# ==> NC */ |
| 34 | PAD_NC(GPP_D7, NONE), |
| 35 | /* D8 : SRCCLKREQ3# ==> NC */ |
| 36 | PAD_NC(GPP_D8, NONE), |
David Wu | 93a6c39 | 2021-08-12 17:45:44 +0800 | [diff] [blame] | 37 | /* D18 : UART1_TXD ==> NC */ |
| 38 | PAD_NC(GPP_D18, NONE), |
| 39 | |
| 40 | /* E0 : SATAXPCIE0 ==> NC */ |
| 41 | PAD_NC(GPP_E0, NONE), |
| 42 | /* E3 : PROC_GP0 ==> SAR1_INT_L */ |
| 43 | PAD_CFG_GPI_APIC(GPP_E3, NONE, PLTRST, LEVEL, NONE), |
| 44 | /* E7 : PROC_GP1 ==> NC */ |
| 45 | PAD_NC(GPP_E7, NONE), |
| 46 | /* E10 : THC0_SPI1_CS# ==> NC */ |
| 47 | PAD_NC(GPP_E10, NONE), |
| 48 | /* E17 : THC0_SPI1_INT# ==> NC */ |
| 49 | PAD_NC(GPP_E17, NONE), |
| 50 | /* E22 : DDPA_CTRLCLK ==> NC */ |
| 51 | PAD_NC(GPP_E22, NONE), |
| 52 | /* E23 : DDPA_CTRLDATA ==> NC */ |
| 53 | PAD_NC(GPP_E23, NONE), |
| 54 | |
| 55 | /* F6 : CNV_PA_BLANKING ==> NC */ |
| 56 | PAD_NC(GPP_F6, NONE), |
David Wu | 93a6c39 | 2021-08-12 17:45:44 +0800 | [diff] [blame] | 57 | /* F21 : EXT_PWR_GATE2# ==> NC */ |
| 58 | PAD_NC(GPP_F21, NONE), |
| 59 | |
| 60 | /* H8 : I2C4_SDA ==> NC */ |
| 61 | PAD_NC(GPP_H8, NONE), |
| 62 | /* H9 : I2C4_SCL ==> NC */ |
| 63 | PAD_NC(GPP_H9, NONE), |
| 64 | /* H12 : I2C7_SDA ==> NC */ |
| 65 | PAD_NC(GPP_H12, NONE), |
| 66 | /* H13 : I2C7_SCL ==> NC */ |
| 67 | PAD_NC(GPP_H13, NONE), |
David Wu | 93a6c39 | 2021-08-12 17:45:44 +0800 | [diff] [blame] | 68 | /* H19 : SRCCLKREQ4# ==> NC */ |
| 69 | PAD_NC(GPP_H19, NONE), |
| 70 | /* H20 : IMGCLKOUT1 ==> NC */ |
| 71 | PAD_NC(GPP_H20, NONE), |
| 72 | /* H21 : IMGCLKOUT2 ==> NC */ |
| 73 | PAD_NC(GPP_H21, NONE), |
| 74 | /* H22 : IMGCLKOUT3 ==> NC */ |
| 75 | PAD_NC(GPP_H22, NONE), |
| 76 | /* H23 : SRCCLKREQ5# ==> NC */ |
| 77 | PAD_NC(GPP_H23, NONE), |
| 78 | |
David Wu | 7181cd2 | 2021-08-27 17:49:05 +0800 | [diff] [blame] | 79 | /* R4 : HDA_RST# ==> DMIC_CLK0_R */ |
| 80 | PAD_CFG_NF(GPP_R4, NONE, DEEP, NF3), |
| 81 | /* R5 : HDA_SDI1 ==> DMIC_DATA0_R */ |
| 82 | PAD_CFG_NF(GPP_R5, NONE, DEEP, NF3), |
| 83 | /* R6 : I2S2_TXD ==> DMIC_CLK1_R */ |
David Wu | a3260fd | 2021-11-03 12:31:06 +0800 | [diff] [blame] | 84 | PAD_CFG_NF(GPP_R6, NONE, DEEP, NF3), |
David Wu | 7181cd2 | 2021-08-27 17:49:05 +0800 | [diff] [blame] | 85 | /* R7 : I2S2_RXD ==> DMIC_DATA1_R */ |
David Wu | a3260fd | 2021-11-03 12:31:06 +0800 | [diff] [blame] | 86 | PAD_CFG_NF(GPP_R7, NONE, DEEP, NF3), |
David Wu | 7181cd2 | 2021-08-27 17:49:05 +0800 | [diff] [blame] | 87 | |
| 88 | /* S0 : SNDW0_CLK ==> I2S1_SPKR_SCLK_R */ |
David Wu | a3260fd | 2021-11-03 12:31:06 +0800 | [diff] [blame] | 89 | PAD_CFG_NF(GPP_S0, NONE, DEEP, NF4), |
David Wu | 7181cd2 | 2021-08-27 17:49:05 +0800 | [diff] [blame] | 90 | /* S1 : SNDW0_DATA ==> I2S1_SPKR_SFRM_R */ |
David Wu | a3260fd | 2021-11-03 12:31:06 +0800 | [diff] [blame] | 91 | PAD_CFG_NF(GPP_S1, NONE, DEEP, NF4), |
David Wu | 7181cd2 | 2021-08-27 17:49:05 +0800 | [diff] [blame] | 92 | /* S2 : SNDW1_CLK ==> I2S1_PCH_TX_SPKR_RX_R */ |
David Wu | a3260fd | 2021-11-03 12:31:06 +0800 | [diff] [blame] | 93 | PAD_CFG_NF(GPP_S2, NONE, DEEP, NF4), |
David Wu | 7181cd2 | 2021-08-27 17:49:05 +0800 | [diff] [blame] | 94 | /* S3 : SNDW1_DATA ==> I2S1_PCH_RX_SPKR_TX */ |
David Wu | a3260fd | 2021-11-03 12:31:06 +0800 | [diff] [blame] | 95 | PAD_CFG_NF(GPP_S3, NONE, DEEP, NF4), |
David Wu | 7181cd2 | 2021-08-27 17:49:05 +0800 | [diff] [blame] | 96 | |
David Wu | 93a6c39 | 2021-08-12 17:45:44 +0800 | [diff] [blame] | 97 | /* GPD11: LANPHYC ==> NC */ |
| 98 | PAD_NC(GPD11, NONE), |
| 99 | }; |
| 100 | |
| 101 | /* Early pad configuration in bootblock */ |
| 102 | static const struct pad_config early_gpio_table[] = { |
| 103 | /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ |
| 104 | PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), |
David Wu | 2d2cc0d | 2021-10-12 13:19:35 +0800 | [diff] [blame] | 105 | /* B4 : PROC_GP3 ==> SSD_PERST_L */ |
| 106 | PAD_CFG_GPO(GPP_B4, 0, DEEP), |
David Wu | 93a6c39 | 2021-08-12 17:45:44 +0800 | [diff] [blame] | 107 | /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ |
| 108 | PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2), |
| 109 | /* B8 : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */ |
| 110 | PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2), |
| 111 | /* |
| 112 | * D1 : ISH_GP1 ==> FP_RST_ODL |
| 113 | * FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down. |
| 114 | * To ensure proper power sequencing for the FPMCU device, reset signal is driven low |
| 115 | * early on in bootblock, followed by enabling of power. Reset signal is deasserted |
| 116 | * later on in ramstage. Since reset signal is asserted in bootblock, it results in |
| 117 | * FPMCU not working after a S3 resume. This is a known issue. |
| 118 | */ |
| 119 | PAD_CFG_GPO(GPP_D1, 0, DEEP), |
| 120 | /* D2 : ISH_GP2 ==> EN_FP_PWR */ |
| 121 | PAD_CFG_GPO(GPP_D2, 1, DEEP), |
David Wu | 2d2cc0d | 2021-10-12 13:19:35 +0800 | [diff] [blame] | 122 | /* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */ |
| 123 | PAD_CFG_GPO(GPP_D11, 1, DEEP), |
David Wu | 93a6c39 | 2021-08-12 17:45:44 +0800 | [diff] [blame] | 124 | /* E0 : SATAXPCIE0 ==> NC */ |
| 125 | PAD_NC(GPP_E0, NONE), |
| 126 | /* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */ |
| 127 | PAD_CFG_GPI(GPP_E13, NONE, DEEP), |
| 128 | /* E15 : RSVD_TP ==> PCH_WP_OD */ |
| 129 | PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), |
Tim Wawrzynczak | 36721a4 | 2021-10-07 16:02:11 -0600 | [diff] [blame] | 130 | /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ |
| 131 | PAD_CFG_GPI(GPP_F18, NONE, DEEP), |
David Wu | 93a6c39 | 2021-08-12 17:45:44 +0800 | [diff] [blame] | 132 | /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */ |
| 133 | PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), |
| 134 | /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ |
| 135 | PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), |
David Wu | 4ceac30 | 2021-09-23 19:21:49 +0800 | [diff] [blame] | 136 | |
| 137 | /* CPU PCIe VGPIO for PEG60 */ |
| 138 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, DEEP, NF1), |
| 139 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, DEEP, NF1), |
| 140 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, DEEP, NF1), |
| 141 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, DEEP, NF1), |
| 142 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, DEEP, NF1), |
| 143 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, DEEP, NF1), |
| 144 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, DEEP, NF1), |
| 145 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, DEEP, NF1), |
| 146 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, DEEP, NF1), |
| 147 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, DEEP, NF1), |
| 148 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, DEEP, NF1), |
| 149 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, DEEP, NF1), |
| 150 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, DEEP, NF1), |
| 151 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, DEEP, NF1), |
| 152 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, DEEP, NF1), |
| 153 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, DEEP, NF1), |
| 154 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, DEEP, NF1), |
| 155 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, DEEP, NF1), |
| 156 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, DEEP, NF1), |
| 157 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, DEEP, NF1), |
David Wu | 93a6c39 | 2021-08-12 17:45:44 +0800 | [diff] [blame] | 158 | }; |
| 159 | |
David Wu | 2d2cc0d | 2021-10-12 13:19:35 +0800 | [diff] [blame] | 160 | static const struct pad_config romstage_gpio_table[] = { |
| 161 | /* B4 : PROC_GP3 ==> SSD_PERST_L */ |
| 162 | PAD_CFG_GPO(GPP_B4, 1, DEEP), |
| 163 | }; |
| 164 | |
David Wu | 93a6c39 | 2021-08-12 17:45:44 +0800 | [diff] [blame] | 165 | const struct pad_config *variant_gpio_override_table(size_t *num) |
| 166 | { |
| 167 | *num = ARRAY_SIZE(override_gpio_table); |
| 168 | return override_gpio_table; |
| 169 | } |
| 170 | |
| 171 | const struct pad_config *variant_early_gpio_table(size_t *num) |
| 172 | { |
| 173 | *num = ARRAY_SIZE(early_gpio_table); |
| 174 | return early_gpio_table; |
| 175 | } |
David Wu | 2d2cc0d | 2021-10-12 13:19:35 +0800 | [diff] [blame] | 176 | |
| 177 | const struct pad_config *variant_romstage_gpio_table(size_t *num) |
| 178 | { |
| 179 | *num = ARRAY_SIZE(romstage_gpio_table); |
| 180 | return romstage_gpio_table; |
| 181 | } |