| Shilpa Sreeramalu | 91a192f | 2015-06-22 21:54:51 +0530 | [diff] [blame^] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2014 Google Inc. |
| 5 | * Copyright (C) 2015 Intel Corporation. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc. |
| 19 | */ |
| 20 | |
| 21 | /* CPU */ |
| 22 | #define DPTF_CPU_PASSIVE 80 |
| 23 | #define DPTF_CPU_CRITICAL 90 |
| 24 | #define DPTF_CPU_ACTIVE_AC0 90 |
| 25 | #define DPTF_CPU_ACTIVE_AC1 80 |
| 26 | #define DPTF_CPU_ACTIVE_AC2 70 |
| 27 | #define DPTF_CPU_ACTIVE_AC3 60 |
| 28 | #define DPTF_CPU_ACTIVE_AC4 50 |
| 29 | |
| 30 | #define DPTF_TSR0_SENSOR_ID 0 |
| 31 | #define DPTF_TSR0_SENSOR_NAME "TMP432_Internal" |
| 32 | #define DPTF_TSR0_PASSIVE 48 |
| 33 | #define DPTF_TSR0_CRITICAL 70 |
| 34 | |
| 35 | #define DPTF_TSR1_SENSOR_ID 1 |
| 36 | #define DPTF_TSR1_SENSOR_NAME "TMP432_Power_top" |
| 37 | #define DPTF_TSR1_PASSIVE 60 |
| 38 | #define DPTF_TSR1_CRITICAL 70 |
| 39 | |
| 40 | #define DPTF_TSR2_SENSOR_ID 2 |
| 41 | #define DPTF_TSR2_SENSOR_NAME "TMP432_CPU_bottom" |
| 42 | #define DPTF_TSR2_PASSIVE 55 |
| 43 | #define DPTF_TSR2_CRITICAL 70 |
| 44 | |
| 45 | #define DPTF_ENABLE_CHARGER |
| 46 | |
| 47 | /* Charger performance states, board-specific values from charger and EC */ |
| 48 | Name (CHPS, Package () { |
| 49 | Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */ |
| 50 | Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ |
| 51 | Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ |
| 52 | Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ |
| 53 | Package () { 0, 0, 0, 0, 0, 0x000, "mA", 0 }, /* 0.0A */ |
| 54 | }) |
| 55 | |
| 56 | /* Mainboard specific _PDL is 1GHz */ |
| 57 | Name (MPDL, 8) |
| 58 | |
| 59 | Name (DTRT, Package () { |
| 60 | /* CPU Throttle Effect on CPU */ |
| 61 | Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 50, 0, 0, 0, 0 }, |
| 62 | |
| 63 | /* CPU Effect on Temp Sensor 0 */ |
| 64 | Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 }, |
| 65 | |
| 66 | #ifdef DPTF_ENABLE_CHARGER |
| 67 | /* Charger Effect on Temp Sensor 1 */ |
| 68 | Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 200, 600, 0, 0, 0, 0 }, |
| 69 | #endif |
| 70 | |
| 71 | /* CPU Effect on Temp Sensor 1 */ |
| 72 | Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR1, 100, 600, 0, 0, 0, 0 }, |
| 73 | |
| 74 | /* CPU Effect on Temp Sensor 2 */ |
| 75 | Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 }, |
| 76 | }) |
| 77 | |
| 78 | Name (MPPC, Package () |
| 79 | { |
| 80 | 0x2, /* Revision */ |
| 81 | Package () { /* Power Limit 1 */ |
| 82 | 0, /* PowerLimitIndex, 0 for Power Limit 1 */ |
| 83 | 1600, /* PowerLimitMinimum */ |
| 84 | 6000, /* PowerLimitMaximum */ |
| 85 | 1000, /* TimeWindowMinimum */ |
| 86 | 1000, /* TimeWindowMaximum */ |
| 87 | 200 /* StepSize */ |
| 88 | }, |
| 89 | Package () { /* Power Limit 2 */ |
| 90 | 1, /* PowerLimitIndex, 1 for Power Limit 2 */ |
| 91 | 8000, /* PowerLimitMinimum */ |
| 92 | 8000, /* PowerLimitMaximum */ |
| 93 | 1000, /* TimeWindowMinimum */ |
| 94 | 1000, /* TimeWindowMaximum */ |
| 95 | 1000 /* StepSize */ |
| 96 | } |
| 97 | }) |
| 98 | |
| 99 | /* Include DPTF */ |
| 100 | #include <soc/intel/skylake/acpi/dptf/dptf.asl> |