Angel Pons | 4b42983 | 2020-04-02 23:48:50 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 2 | |
| 3 | #ifndef RAMINIT_H |
| 4 | #define RAMINIT_H |
| 5 | |
Angel Pons | 95de231 | 2020-02-17 13:08:53 +0100 | [diff] [blame] | 6 | #include "ironlake.h" |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 7 | |
Angel Pons | 7a87c92 | 2021-01-15 22:50:41 +0100 | [diff] [blame] | 8 | #define NUM_CHANNELS 2 |
| 9 | #define NUM_SLOTS 2 |
| 10 | #define NUM_RANKS 2 |
| 11 | |
| 12 | /* [REG_178][CHANNEL][2 * SLOT + RANK][LANE] */ |
| 13 | typedef struct { |
| 14 | u8 smallest; |
| 15 | u8 largest; |
| 16 | } timing_bounds_t[2][2][2][9]; |
| 17 | |
| 18 | #define MRC_CACHE_VERSION 3 |
| 19 | |
| 20 | struct ram_training { |
| 21 | /* [TM][CHANNEL][SLOT][RANK][LANE] */ |
| 22 | u16 lane_timings[4][2][2][2][9]; |
| 23 | u16 reg_178; |
| 24 | u16 reg_10b; |
| 25 | |
| 26 | u8 reg178_center; |
| 27 | u8 reg178_smallest; |
| 28 | u8 reg178_largest; |
| 29 | timing_bounds_t timing_bounds[2]; |
| 30 | u16 timing_offset[2][2][2][9]; |
| 31 | u16 timing2_offset[2][2][2][9]; |
| 32 | u16 timing2_bounds[2][2][2][9][2]; |
| 33 | u8 reg274265[2][3]; /* [CHANNEL][REGISTER] */ |
| 34 | u8 reg2ca9_bit0; |
| 35 | u32 reg_6dc; |
| 36 | u32 reg_6e8; |
| 37 | }; |
| 38 | |
| 39 | struct raminfo { |
| 40 | u16 clock_speed_index; /* clock_speed (REAL, not DDR) / 133.(3) - 3 */ |
| 41 | u16 fsb_frequency; /* in 1.(1)/2 MHz. */ |
| 42 | u8 is_x16_module[2][2]; /* [CHANNEL][SLOT] */ |
| 43 | u8 density[2][2]; /* [CHANNEL][SLOT] */ |
| 44 | u8 populated_ranks[2][2][2]; /* [CHANNEL][SLOT][RANK] */ |
| 45 | int rank_start[2][2][2]; |
| 46 | u8 cas_latency; |
| 47 | u8 board_lane_delay[9]; |
| 48 | u8 use_ecc; |
| 49 | u8 revision; |
| 50 | u8 max_supported_clock_speed_index; |
| 51 | u8 uma_enabled; |
| 52 | u8 spd[2][2][151]; /* [CHANNEL][SLOT][BYTE] */ |
| 53 | u8 silicon_revision; |
| 54 | u8 populated_ranks_mask[2]; |
| 55 | u8 max_slots_used_in_channel; |
| 56 | u8 mode4030[2]; |
| 57 | u16 avg4044[2]; |
| 58 | u16 max4048[2]; |
| 59 | unsigned int total_memory_mb; |
| 60 | unsigned int interleaved_part_mb; |
| 61 | unsigned int non_interleaved_part_mb; |
| 62 | |
| 63 | unsigned int memory_reserved_for_heci_mb; |
| 64 | |
| 65 | struct ram_training training; |
| 66 | u32 last_500_command[2]; |
| 67 | |
| 68 | u32 delay46_ps[2]; |
| 69 | u32 delay54_ps[2]; |
| 70 | u8 revision_flag_1; |
| 71 | u8 some_delay_1_cycle_floor; |
| 72 | u8 some_delay_2_halfcycles_ceil; |
| 73 | u8 some_delay_3_ps_rounded; |
| 74 | |
| 75 | const struct ram_training *cached_training; |
| 76 | }; |
| 77 | |
| 78 | static inline unsigned int fsbcycle_ps(struct raminfo *info) |
| 79 | { |
| 80 | return 900000 / info->fsb_frequency; |
| 81 | } |
| 82 | |
| 83 | /* The time of DDR transfer in ps. */ |
| 84 | static inline unsigned int halfcycle_ps(struct raminfo *info) |
| 85 | { |
| 86 | return 3750 / (info->clock_speed_index + 3); |
| 87 | } |
| 88 | |
| 89 | /* Frequency in 1.(1)=10/9 MHz units. */ |
| 90 | static inline unsigned int frequency_11(struct raminfo *info) |
| 91 | { |
| 92 | return (info->clock_speed_index + 3) * 120; |
| 93 | } |
| 94 | |
Vladimir Serbinenko | 9817a37 | 2014-02-19 22:07:12 +0100 | [diff] [blame] | 95 | void chipset_init(const int s3resume); |
Vladimir Serbinenko | 902626c | 2014-02-16 17:22:26 +0100 | [diff] [blame] | 96 | /* spd_addrmap is array of 4 elements: |
| 97 | Channel 0 Slot 0 |
| 98 | Channel 0 Slot 1 |
| 99 | Channel 1 Slot 0 |
| 100 | Channel 1 Slot 1 |
| 101 | 0 means "not present" |
| 102 | */ |
| 103 | void raminit(const int s3resume, const u8 *spd_addrmap); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 104 | |
Angel Pons | 7a87c92 | 2021-01-15 22:50:41 +0100 | [diff] [blame] | 105 | u16 get_max_timing(struct raminfo *info, int channel); |
Angel Pons | a8b8271 | 2021-01-15 23:39:02 +0100 | [diff] [blame] | 106 | void early_quickpath_init(const u8 x2ca8); |
Angel Pons | 7a87c92 | 2021-01-15 22:50:41 +0100 | [diff] [blame] | 107 | void late_quickpath_init(struct raminfo *info, const int s3resume); |
| 108 | |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 109 | #endif /* RAMINIT_H */ |