zbao | 246e84b | 2012-07-13 18:47:03 +0800 | [diff] [blame] | 1 | ## |
| 2 | ## This file is part of the coreboot project. |
| 3 | ## |
| 4 | ## Copyright (C) 2010 Advanced Micro Devices, Inc. |
| 5 | ## |
| 6 | ## This program is free software; you can redistribute it and/or modify |
| 7 | ## it under the terms of the GNU General Public License as published by |
| 8 | ## the Free Software Foundation; version 2 of the License. |
| 9 | ## |
| 10 | ## This program is distributed in the hope that it will be useful, |
| 11 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | ## GNU General Public License for more details. |
| 14 | ## |
| 15 | ## You should have received a copy of the GNU General Public License |
| 16 | ## along with this program; if not, write to the Free Software |
Paul Menzel | a46a712 | 2013-02-23 18:37:27 +0100 | [diff] [blame] | 17 | ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
zbao | 246e84b | 2012-07-13 18:47:03 +0800 | [diff] [blame] | 18 | ## |
| 19 | |
| 20 | config SOUTHBRIDGE_AMD_AGESA_HUDSON |
| 21 | bool |
| 22 | select IOAPIC |
| 23 | select HAVE_USBDEBUG |
Kyösti Mälkki | 56892fc | 2013-06-16 17:12:37 +0300 | [diff] [blame] | 24 | select HAVE_HARD_RESET |
zbao | 246e84b | 2012-07-13 18:47:03 +0800 | [diff] [blame] | 25 | |
Siyuan Wang | 9157145 | 2013-07-09 17:32:42 +0800 | [diff] [blame^] | 26 | config SOUTHBRIDGE_AMD_AGESA_YANGTZE |
| 27 | bool |
| 28 | select IOAPIC |
| 29 | select HAVE_USBDEBUG |
| 30 | select HAVE_HARD_RESET |
| 31 | |
| 32 | if SOUTHBRIDGE_AMD_AGESA_HUDSON || SOUTHBRIDGE_AMD_AGESA_YANGTZE |
Kyösti Mälkki | 59d0d15 | 2013-06-11 16:30:48 +0300 | [diff] [blame] | 33 | |
zbao | 246e84b | 2012-07-13 18:47:03 +0800 | [diff] [blame] | 34 | config BOOTBLOCK_SOUTHBRIDGE_INIT |
| 35 | string |
| 36 | default "southbridge/amd/agesa/hudson/bootblock.c" |
zbao | 246e84b | 2012-07-13 18:47:03 +0800 | [diff] [blame] | 37 | |
| 38 | config SOUTHBRIDGE_AMD_HUDSON_SKIP_ISA_DMA_INIT |
| 39 | bool |
| 40 | default n |
zbao | 246e84b | 2012-07-13 18:47:03 +0800 | [diff] [blame] | 41 | |
| 42 | config EHCI_BAR |
| 43 | hex |
Kyösti Mälkki | 59d0d15 | 2013-06-11 16:30:48 +0300 | [diff] [blame] | 44 | default 0xfef00000 |
zbao | 246e84b | 2012-07-13 18:47:03 +0800 | [diff] [blame] | 45 | |
| 46 | config EHCI_DEBUG_OFFSET |
| 47 | hex |
Kyösti Mälkki | 59d0d15 | 2013-06-11 16:30:48 +0300 | [diff] [blame] | 48 | default 0xe0 |
zbao | 246e84b | 2012-07-13 18:47:03 +0800 | [diff] [blame] | 49 | |
Dave Frodin | 1fa1904 | 2013-06-14 07:11:40 -0600 | [diff] [blame] | 50 | config HUDSON_XHCI_ENABLE |
| 51 | bool "Enable Hudson XHCI Controller" |
| 52 | default y |
| 53 | help |
| 54 | The XHCI controller must be enabled and the XHCI firmware |
| 55 | must be added in order to have USB 3.0 support configured |
| 56 | by coreboot. The OS will be responsible for enabling the XHCI |
| 57 | controller if the the XHCI firmware is available but the |
| 58 | XHCI controller is not enabled by coreboot. |
| 59 | |
zbao | 246e84b | 2012-07-13 18:47:03 +0800 | [diff] [blame] | 60 | config HUDSON_XHCI_FWM |
| 61 | bool "Add xhci firmware" |
| 62 | default y |
Dave Frodin | 1fa1904 | 2013-06-14 07:11:40 -0600 | [diff] [blame] | 63 | help |
| 64 | Add Hudson 2/3/4 XHCI Firmware to support the onboard USB 3.0 |
zbao | 246e84b | 2012-07-13 18:47:03 +0800 | [diff] [blame] | 65 | |
| 66 | config HUDSON_IMC_FWM |
| 67 | bool "Add imc firmware" |
| 68 | default y |
| 69 | help |
| 70 | Add Hudson 2/3/4 IMC Firmware to support the onboard fan control |
zbao | 246e84b | 2012-07-13 18:47:03 +0800 | [diff] [blame] | 71 | |
| 72 | config HUDSON_GEC_FWM |
Bruce Griffith | 5c2025c | 2013-04-23 14:31:55 -0600 | [diff] [blame] | 73 | bool |
zbao | 246e84b | 2012-07-13 18:47:03 +0800 | [diff] [blame] | 74 | default n |
| 75 | help |
Bruce Griffith | 5c2025c | 2013-04-23 14:31:55 -0600 | [diff] [blame] | 76 | Add Hudson 2/3/4 GEC Firmware to support the onboard gigabit Ethernet MAC. |
| 77 | Must be connected to a Broadcom B50610 or B50610M PHY on the motherboard. |
zbao | 246e84b | 2012-07-13 18:47:03 +0800 | [diff] [blame] | 78 | |
| 79 | config HUDSON_XHCI_FWM_FILE |
| 80 | string "XHCI firmware path and filename" |
Siyuan Wang | 9157145 | 2013-07-09 17:32:42 +0800 | [diff] [blame^] | 81 | default "3rdparty/southbridge/amd/hudson/xhci.bin" if SOUTHBRIDGE_AMD_AGESA_HUDSON |
| 82 | default "3rdparty/southbridge/amd/yangtze/xhci.bin" if SOUTHBRIDGE_AMD_AGESA_YANGTZE |
zbao | 246e84b | 2012-07-13 18:47:03 +0800 | [diff] [blame] | 83 | depends on HUDSON_XHCI_FWM |
| 84 | |
| 85 | config HUDSON_IMC_FWM_FILE |
| 86 | string "IMC firmware path and filename" |
Siyuan Wang | 9157145 | 2013-07-09 17:32:42 +0800 | [diff] [blame^] | 87 | default "3rdparty/southbridge/amd/hudson/imc.bin" if SOUTHBRIDGE_AMD_AGESA_HUDSON |
| 88 | default "3rdparty/southbridge/amd/yangtze/imc.bin" if SOUTHBRIDGE_AMD_AGESA_YANGTZE |
zbao | 246e84b | 2012-07-13 18:47:03 +0800 | [diff] [blame] | 89 | depends on HUDSON_IMC_FWM |
| 90 | |
| 91 | config HUDSON_GEC_FWM_FILE |
| 92 | string "GEC firmware path and filename" |
Siyuan Wang | 9157145 | 2013-07-09 17:32:42 +0800 | [diff] [blame^] | 93 | default "3rdparty/southbridge/amd/hudson/gec.bin" if SOUTHBRIDGE_AMD_AGESA_HUDSON |
| 94 | default "3rdparty/southbridge/amd/yangtze/gec.bin" if SOUTHBRIDGE_AMD_AGESA_YANGTZE |
zbao | 246e84b | 2012-07-13 18:47:03 +0800 | [diff] [blame] | 95 | depends on HUDSON_GEC_FWM |
| 96 | |
| 97 | config HUDSON_FWM |
| 98 | bool |
| 99 | default y if HUDSON_XHCI_FWM || HUDSON_IMC_FWM || HUDSON_GEC_FWM |
| 100 | default n if !HUDSON_XHCI_FWM && !HUDSON_IMC_FWM && !HUDSON_GEC_FWM |
| 101 | |
| 102 | if HUDSON_FWM |
| 103 | |
| 104 | config HUDSON_FWM_POSITION |
| 105 | hex "Hudson Firmware rom Position" |
| 106 | default 0xFFF20000 if BOARD_ROMSIZE_KB_1024 |
| 107 | default 0xFFE20000 if BOARD_ROMSIZE_KB_2048 |
| 108 | default 0xFFC20000 if BOARD_ROMSIZE_KB_4096 |
| 109 | default 0xFF820000 if BOARD_ROMSIZE_KB_8192 |
| 110 | default 0xFF020000 if BOARD_ROMSIZE_KB_16384 |
| 111 | help |
Dave Frodin | b578627 | 2012-11-06 13:37:08 -0700 | [diff] [blame] | 112 | Hudson requires the firmware MUST be located at |
zbao | 246e84b | 2012-07-13 18:47:03 +0800 | [diff] [blame] | 113 | a specific address (ROM start address + 0x20000), otherwise |
| 114 | xhci host Controller can not find or load the xhci firmware. |
| 115 | |
| 116 | The firmware start address is dependent on the ROM chip size. |
| 117 | The default offset is 0x20000 from the ROM start address, namely |
Dave Frodin | b578627 | 2012-11-06 13:37:08 -0700 | [diff] [blame] | 118 | 0xFFF20000 if flash chip size is 1M |
| 119 | 0xFFE20000 if flash chip size is 2M |
| 120 | 0xFFC20000 if flash chip size is 4M |
| 121 | 0xFF820000 if flash chip size is 8M |
| 122 | 0xFF020000 if flash chip size is 16M |
Martin Roth | 80e3516 | 2013-01-21 19:33:22 -0700 | [diff] [blame] | 123 | endif # HUDSON_FWM |
zbao | 246e84b | 2012-07-13 18:47:03 +0800 | [diff] [blame] | 124 | |
| 125 | choice |
| 126 | prompt "SATA Mode" |
| 127 | default HUDSON_SATA_IDE |
| 128 | help |
| 129 | Select the mode in which SATA should be driven. NATIVE AHCI, or RAID. |
| 130 | The default is NATIVE. |
| 131 | |
| 132 | config HUDSON_SATA_IDE |
| 133 | bool "NATIVE" |
| 134 | help |
| 135 | NATIVE is the default mode and does not require a ROM. |
| 136 | |
| 137 | config HUDSON_SATA_RAID |
| 138 | bool "RAID" |
| 139 | help |
| 140 | HUDSON RAID mode must have the two required ROM files. |
| 141 | |
| 142 | config HUDSON_SATA_AHCI |
| 143 | bool "AHCI" |
| 144 | help |
| 145 | AHCI may work with or without AHCI ROM. It depends on the payload support. |
| 146 | For example, seabios does not require the AHCI ROM. |
| 147 | |
| 148 | config HUDSON_SATA_LEGACY_IDE |
| 149 | bool "LEGACY IDE" |
| 150 | help |
| 151 | TODO |
| 152 | |
| 153 | config HUDSON_SATA_IDE2AHCI |
| 154 | bool "IDE to AHCI" |
| 155 | help |
| 156 | TODO |
| 157 | |
| 158 | config HUDSON_SATA_AHCI7804 |
| 159 | bool "AHCI7804" |
| 160 | help |
| 161 | AHCI ROM Required, and AMD driver required in the OS. |
| 162 | |
| 163 | config HUDSON_SATA_IDE2AHCI7804 |
| 164 | bool "IDE to AHCI7804" |
| 165 | help |
| 166 | AHCI ROM Required, and AMD driver required in the OS. |
| 167 | endchoice |
| 168 | |
| 169 | config HUDSON_SATA_MODE |
| 170 | hex |
| 171 | depends on (HUDSON_SATA_IDE || HUDSON_SATA_RAID || HUDSON_SATA_AHCI) |
| 172 | default "0x0" if HUDSON_SATA_IDE |
| 173 | default "0x1" if HUDSON_SATA_RAID |
| 174 | default "0x2" if HUDSON_SATA_AHCI |
| 175 | default "0x3" if HUDSON_SATA_LEGACY_IDE |
| 176 | default "0x4" if HUDSON_SATA_IDE2AHCI |
| 177 | default "0x5" if HUDSON_SATA_AHCI7804 |
| 178 | default "0x6" if HUDSON_SATA_IDE2AHCI7804 |
| 179 | |
| 180 | if HUDSON_SATA_AHCI || HUDSON_SATA_AHCI7804 |
| 181 | config AHCI_ROM_ID |
| 182 | string "AHCI device PCI IDs" |
| 183 | default "1022,7801" if HUDSON_SATA_AHCI |
| 184 | default "1022,7804" if HUDSON_SATA_AHCI7804 |
| 185 | |
| 186 | config HUDSON_AHCI_ROM |
| 187 | bool "Add a AHCI ROM" |
| 188 | |
| 189 | config AHCI_ROM_FILE |
| 190 | string "AHCI ROM path and filename" |
| 191 | depends on HUDSON_AHCI_ROM |
| 192 | default "src/southbridge/amd/agesa/hudson/ahci.bin" |
Martin Roth | 80e3516 | 2013-01-21 19:33:22 -0700 | [diff] [blame] | 193 | endif # HUDSON_SATA_AHCI || HUDSON_SATA_AHCI7804 |
zbao | 246e84b | 2012-07-13 18:47:03 +0800 | [diff] [blame] | 194 | |
| 195 | if HUDSON_SATA_RAID |
| 196 | config RAID_ROM_ID |
| 197 | string "RAID device PCI IDs" |
| 198 | default "1022,7802" |
| 199 | help |
| 200 | 1022,7802 for SATA NON-RAID5 module, 1022,7803 for SATA RAID5 mode |
| 201 | |
| 202 | config RAID_ROM_FILE |
| 203 | string "RAID ROM path and filename" |
| 204 | depends on HUDSON_SATA_RAID |
| 205 | default "src/southbridge/amd/agesa/hudson/raid.bin" |
| 206 | |
| 207 | config RAID_MISC_ROM_FILE |
| 208 | string "RAID Misc ROM path and filename" |
| 209 | default "src/southbridge/amd/agesa/hudson/misc.bin" |
| 210 | depends on HUDSON_SATA_RAID |
| 211 | |
| 212 | config RAID_MISC_ROM_POSITION |
| 213 | hex "RAID Misc ROM Position" |
| 214 | default 0xFFF00000 |
| 215 | depends on HUDSON_SATA_RAID |
| 216 | help |
| 217 | The RAID ROM requires that the MISC ROM is located between the range |
| 218 | 0xFFF0_0000 to 0xFFF0_FFFF. Also, it must 1K bytes aligned. |
| 219 | The CONFIG_ROM_SIZE must larger than 0x100000. |
Martin Roth | 80e3516 | 2013-01-21 19:33:22 -0700 | [diff] [blame] | 220 | endif # HUDSON_SATA_RAID |
zbao | 246e84b | 2012-07-13 18:47:03 +0800 | [diff] [blame] | 221 | |
Zheng Bao | f57d0dc | 2013-02-17 17:01:34 +0800 | [diff] [blame] | 222 | config S3_DATA_POS |
Zheng Bao | eb1d39b | 2012-08-27 17:45:01 +0800 | [diff] [blame] | 223 | hex "S3 volatile storage position" |
| 224 | default 0xFFFF0000 |
| 225 | depends on HAVE_ACPI_RESUME |
| 226 | help |
| 227 | For a system with S3 feature, the BIOS needs to save some data to |
Zheng Bao | 178df11 | 2013-02-17 16:41:14 +0800 | [diff] [blame] | 228 | non-volatile storage at cold boot stage. |
Zheng Bao | eb1d39b | 2012-08-27 17:45:01 +0800 | [diff] [blame] | 229 | |
Zheng Bao | 22ec9f9 | 2013-02-18 16:56:09 +0800 | [diff] [blame] | 230 | config S3_DATA_SIZE |
| 231 | int "S3 volatile storage size" |
| 232 | default 32768 |
| 233 | depends on HAVE_ACPI_RESUME |
| 234 | help |
| 235 | For a system with S3 feature, the BIOS needs to save some data to |
| 236 | non-volatile storage at cold boot stage. |
| 237 | |
Martin Roth | eac220f | 2013-01-16 09:07:30 -0700 | [diff] [blame] | 238 | config HUDSON_LEGACY_FREE |
| 239 | bool "System is legacy free" |
| 240 | help |
| 241 | Select y if there is no keyboard controller in the system. |
| 242 | This sets variables in AGESA and ACPI. |
Martin Roth | 80e3516 | 2013-01-21 19:33:22 -0700 | [diff] [blame] | 243 | |
Siyuan Wang | 9157145 | 2013-07-09 17:32:42 +0800 | [diff] [blame^] | 244 | endif # SOUTHBRIDGE_AMD_AGESA_HUDSON || SOUTHBRIDGE_AMD_AGESA_YANGTZE |
| 245 | |
| 246 | if SOUTHBRIDGE_AMD_AGESA_YANGTZE |
| 247 | config AMD_SB_SPI_TX_LEN |
| 248 | int |
| 249 | default 64 |
| 250 | endif |