| Angel Pons | f94ac9a | 2020-04-05 15:46:48 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 2 | |
| 3 | #ifndef _SOC_INTEL_BROADWELL_CHIP_H_ |
| 4 | #define _SOC_INTEL_BROADWELL_CHIP_H_ |
| 5 | |
| Michael Niewöhner | 97e21d3 | 2020-12-28 00:49:33 +0100 | [diff] [blame] | 6 | #include <drivers/intel/gma/gma.h> |
| Elyes HAOUAS | c4e4193 | 2018-11-01 11:29:50 +0100 | [diff] [blame] | 7 | #include <stdint.h> |
| 8 | |
| Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 9 | struct soc_intel_broadwell_config { |
| Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 10 | /* |
| 11 | * Digital Port Hotplug Enable: |
| 12 | * 0x04 = Enabled, 2ms short pulse |
| 13 | * 0x05 = Enabled, 4.5ms short pulse |
| 14 | * 0x06 = Enabled, 6ms short pulse |
| 15 | * 0x07 = Enabled, 100ms short pulse |
| 16 | */ |
| 17 | u8 gpu_dp_b_hotplug; |
| 18 | u8 gpu_dp_c_hotplug; |
| 19 | u8 gpu_dp_d_hotplug; |
| 20 | |
| Michael Niewöhner | 97e21d3 | 2020-12-28 00:49:33 +0100 | [diff] [blame] | 21 | /* IGD panel configuration */ |
| 22 | struct i915_gpu_panel_config panel_cfg; |
| Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 23 | |
| 24 | /* |
| 25 | * Graphics CD Clock Frequency |
| 26 | * 0 = 337.5MHz |
| 27 | * 1 = 450MHz |
| 28 | * 2 = 540MHz |
| 29 | * 3 = 675MHz |
| 30 | */ |
| 31 | int cdclk; |
| 32 | |
| Matt DeVillier | 53e2446 | 2016-08-05 02:20:15 -0500 | [diff] [blame] | 33 | struct i915_gpu_controller_info gfx; |
| Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 34 | }; |
| 35 | |
| Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 36 | #endif |