Kyösti Mälkki | 9116270 | 2011-11-03 15:22:01 +0200 | [diff] [blame^] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2009 coresystems GmbH |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License as |
| 8 | * published by the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | */ |
| 19 | |
| 20 | #include <string.h> |
| 21 | #include <device/pci.h> |
| 22 | #include <arch/acpi.h> |
| 23 | |
| 24 | /* FIXME: This needs to go into a separate .h file |
| 25 | * to be included by the ich7 smi handler, ich7 smi init |
| 26 | * code and the mainboard fadt. |
| 27 | */ |
| 28 | #define APM_CNT 0x0 /* ACPI mode only */ |
| 29 | #define CST_CONTROL 0x85 |
| 30 | #define PST_CONTROL 0x0 |
| 31 | #define ACPI_DISABLE 0xAA |
| 32 | #define ACPI_ENABLE 0x55 |
| 33 | #define S4_BIOS 0x77 |
| 34 | #define GNVS_UPDATE 0xea |
| 35 | |
| 36 | void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) |
| 37 | { |
| 38 | acpi_header_t *header = &(fadt->header); |
| 39 | u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)), 0x40) & 0xfffe; |
| 40 | |
| 41 | memset((void *) fadt, 0, sizeof(acpi_fadt_t)); |
| 42 | memcpy(header->signature, "FACP", 4); |
| 43 | header->length = sizeof(acpi_fadt_t); |
| 44 | header->revision = 4; |
| 45 | memcpy(header->oem_id, OEM_ID, 6); |
| 46 | memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); |
| 47 | memcpy(header->asl_compiler_id, ASLC, 4); |
| 48 | header->asl_compiler_revision = 1; |
| 49 | |
| 50 | fadt->firmware_ctrl = (unsigned long) facs; |
| 51 | fadt->dsdt = (unsigned long) dsdt; |
| 52 | fadt->model = 1; |
| 53 | fadt->preferred_pm_profile = 0; /* PM_MOBILE; */ |
| 54 | |
| 55 | fadt->sci_int = 0x9; |
| 56 | fadt->smi_cmd = APM_CNT; |
| 57 | fadt->acpi_enable = ACPI_ENABLE; |
| 58 | fadt->acpi_disable = ACPI_DISABLE; |
| 59 | fadt->s4bios_req = S4_BIOS; |
| 60 | fadt->pstate_cnt = PST_CONTROL; |
| 61 | |
| 62 | fadt->pm1a_evt_blk = pmbase; |
| 63 | fadt->pm1b_evt_blk = 0x0; |
| 64 | fadt->pm1a_cnt_blk = pmbase + 0x4; |
| 65 | fadt->pm1b_cnt_blk = 0x0; |
| 66 | fadt->pm2_cnt_blk = 0x0; |
| 67 | fadt->pm_tmr_blk = pmbase + 0x8; |
| 68 | fadt->gpe0_blk = pmbase + 0x28; |
| 69 | fadt->gpe1_blk = 0; |
| 70 | |
| 71 | fadt->pm1_evt_len = 4; |
| 72 | fadt->pm1_cnt_len = 2; |
| 73 | // XXX: pm2_cnt_len is probably wrong. find out right value (hint: it's != 0) |
| 74 | fadt->pm2_cnt_len = 0; |
| 75 | fadt->pm_tmr_len = 4; |
| 76 | fadt->gpe0_blk_len = 8; |
| 77 | fadt->gpe1_blk_len = 0; |
| 78 | fadt->gpe1_base = 0; |
| 79 | fadt->cst_cnt = 0; /* CST_CONTROL; */ |
| 80 | fadt->p_lvl2_lat = 1; |
| 81 | fadt->p_lvl3_lat = 85; |
| 82 | fadt->flush_size = 1024; |
| 83 | fadt->flush_stride = 16; |
| 84 | fadt->duty_offset = 1; |
| 85 | fadt->duty_width = 0; |
| 86 | fadt->day_alrm = 0xd; |
| 87 | fadt->mon_alrm = 0x00; |
| 88 | fadt->century = 0x00; |
| 89 | fadt->iapc_boot_arch = 0x03; |
| 90 | |
| 91 | fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | |
| 92 | ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | |
| 93 | ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; |
| 94 | |
| 95 | fadt->reset_reg.space_id = 0; |
| 96 | fadt->reset_reg.bit_width = 0; |
| 97 | fadt->reset_reg.bit_offset = 0; |
| 98 | fadt->reset_reg.resv = 0; |
| 99 | fadt->reset_reg.addrl = 0x0; |
| 100 | fadt->reset_reg.addrh = 0x0; |
| 101 | |
| 102 | fadt->reset_value = 0; |
| 103 | fadt->x_firmware_ctl_l = (unsigned long)facs; |
| 104 | fadt->x_firmware_ctl_h = 0; |
| 105 | fadt->x_dsdt_l = (unsigned long)dsdt; |
| 106 | fadt->x_dsdt_h = 0; |
| 107 | |
| 108 | fadt->x_pm1a_evt_blk.space_id = 1; |
| 109 | fadt->x_pm1a_evt_blk.bit_width = 32; |
| 110 | fadt->x_pm1a_evt_blk.bit_offset = 0; |
| 111 | fadt->x_pm1a_evt_blk.resv = 0; |
| 112 | fadt->x_pm1a_evt_blk.addrl = pmbase; |
| 113 | fadt->x_pm1a_evt_blk.addrh = 0x0; |
| 114 | |
| 115 | fadt->x_pm1b_evt_blk.space_id = 1; |
| 116 | fadt->x_pm1b_evt_blk.bit_width = 0; |
| 117 | fadt->x_pm1b_evt_blk.bit_offset = 0; |
| 118 | fadt->x_pm1b_evt_blk.resv = 0; |
| 119 | fadt->x_pm1b_evt_blk.addrl = 0x0; |
| 120 | fadt->x_pm1b_evt_blk.addrh = 0x0; |
| 121 | |
| 122 | fadt->x_pm1a_cnt_blk.space_id = 1; |
| 123 | fadt->x_pm1a_cnt_blk.bit_width = 16; |
| 124 | fadt->x_pm1a_cnt_blk.bit_offset = 0; |
| 125 | fadt->x_pm1a_cnt_blk.resv = 0; |
| 126 | fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4; |
| 127 | fadt->x_pm1a_cnt_blk.addrh = 0x0; |
| 128 | |
| 129 | fadt->x_pm1b_cnt_blk.space_id = 1; |
| 130 | fadt->x_pm1b_cnt_blk.bit_width = 0; |
| 131 | fadt->x_pm1b_cnt_blk.bit_offset = 0; |
| 132 | fadt->x_pm1b_cnt_blk.resv = 0; |
| 133 | fadt->x_pm1b_cnt_blk.addrl = 0x0; |
| 134 | fadt->x_pm1b_cnt_blk.addrh = 0x0; |
| 135 | |
| 136 | fadt->x_pm2_cnt_blk.space_id = 1; |
| 137 | fadt->x_pm2_cnt_blk.bit_width = 0; |
| 138 | fadt->x_pm2_cnt_blk.bit_offset = 0; |
| 139 | fadt->x_pm2_cnt_blk.resv = 0; |
| 140 | fadt->x_pm2_cnt_blk.addrl = 0x0; |
| 141 | fadt->x_pm2_cnt_blk.addrh = 0x0; |
| 142 | |
| 143 | fadt->x_pm_tmr_blk.space_id = 1; |
| 144 | fadt->x_pm_tmr_blk.bit_width = 32; |
| 145 | fadt->x_pm_tmr_blk.bit_offset = 0; |
| 146 | fadt->x_pm_tmr_blk.resv = 0; |
| 147 | fadt->x_pm_tmr_blk.addrl = pmbase + 0x8; |
| 148 | fadt->x_pm_tmr_blk.addrh = 0x0; |
| 149 | |
| 150 | fadt->x_gpe0_blk.space_id = 1; |
| 151 | fadt->x_gpe0_blk.bit_width = 64; |
| 152 | fadt->x_gpe0_blk.bit_offset = 0; |
| 153 | fadt->x_gpe0_blk.resv = 0; |
| 154 | fadt->x_gpe0_blk.addrl = pmbase + 0x28; |
| 155 | fadt->x_gpe0_blk.addrh = 0x0; |
| 156 | |
| 157 | fadt->x_gpe1_blk.space_id = 1; |
| 158 | fadt->x_gpe1_blk.bit_width = 0; |
| 159 | fadt->x_gpe1_blk.bit_offset = 0; |
| 160 | fadt->x_gpe1_blk.resv = 0; |
| 161 | fadt->x_gpe1_blk.addrl = 0x0; |
| 162 | fadt->x_gpe1_blk.addrh = 0x0; |
| 163 | |
| 164 | header->checksum = |
| 165 | acpi_checksum((void *) fadt, header->length); |
| 166 | } |