| Kyösti Mälkki | 9116270 | 2011-11-03 15:22:01 +0200 | [diff] [blame^] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2011 Kyösti Mälkki <kyosti.malkki@gmail.com> |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | */ |
| 19 | |
| 20 | #ifndef DXPLPLUSU_BUS_H_INCLUDED |
| 21 | #define DXPLPLUSU_BUS_H_INCLUDED |
| 22 | |
| 23 | // These were determined by seeing how coreboot enumerates the various |
| 24 | // PCI (and PCI-like) buses on the board. |
| 25 | |
| 26 | #define PCI_BUS_ROOT 0 |
| 27 | #define PCI_BUS_AGP 1 // AGP |
| 28 | #define PCI_BUS_E7501_HI_B 2 // P64H2#1 |
| 29 | #define PCI_BUS_P64H2_B 3 // P64H2#1 bus B |
| 30 | #define PCI_BUS_P64H2_A 4 // P64H2#1 bus A |
| 31 | #define PCI_BUS_ICH4 5 // ICH4 |
| 32 | |
| 33 | // IOAPIC addresses determined by coreboot enumeration. |
| 34 | // Someday add functions to get APIC IDs and versions from the chips themselves. |
| 35 | |
| 36 | #define IOAPIC_ICH4 2 |
| 37 | #define IOAPIC_P64H2_BUS_B 3 // IOAPIC 3 at 02:1c.0 MBAR = fe300000 DataAddr = fe300010 |
| 38 | #define IOAPIC_P64H2_BUS_A 4 // IOAPIC 4 at 02:1e.0 MBAR = fe301000 DataAddr = fe301010 |
| 39 | |
| 40 | #define INTEL_IOAPIC_NUM_INTERRUPTS 24 // Both ICH-4 and P64-H2 |
| 41 | |
| 42 | #endif |