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review.coreboot.org / coreboot / 910f4ca5c50ef9d1d05c46b3ff52c69d29f745dd / . / src / mainboard / supermicro / h8scm_fam10 / resourcemap.c
blob: 7a3631b26a4deeeedeb4e589a81f3505a5124e20 [file] [log] [blame]
Zheng Bao910f4ca2011-03-28 04:38:14 +0000[diff] [blame^]1/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2010 Advanced Micro Devices, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18 */
19
20
21
22static void setup_mb_resource_map(void)
23{
24 static const unsigned int register_values[] = {
25 /* Careful set limit registers before base registers which contain the enables */
26 /* DRAM Limit i Registers
27 * F1:0x44 i = 0
28 * F1:0x4C i = 1
29 * F1:0x54 i = 2
30 * F1:0x5C i = 3
31 * F1:0x64 i = 4
32 * F1:0x6C i = 5
33 * F1:0x74 i = 6
34 * F1:0x7C i = 7
35 * [ 2: 0] Destination Node ID
36 * 000 = Node 0
37 * 001 = Node 1
38 * 010 = Node 2
39 * 011 = Node 3
40 * 100 = Node 4
41 * 101 = Node 5
42 * 110 = Node 6
43 * 111 = Node 7
44 * [ 7: 3] Reserved
45 * [10: 8] Interleave select
46 * specifies the values of A[14:12] to use with interleave enable.
47 * [15:11] Reserved
48 * [31:16] DRAM Limit Address i Bits 39-24
49 * This field defines the upper address bits of a 40 bit address
50 * that define the end of the DRAM region.
51 */
52// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CONFIG_CAR_FAM10
53 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001,
54 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002,
55 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003,
56 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x64), 0x0000f8f8, 0x00000004,
57 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x6C), 0x0000f8f8, 0x00000005,
58 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x74), 0x0000f8f8, 0x00000006,
59 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x7C), 0x0000f8f8, 0x00000007,
60 /* DRAM Base i Registers
61 * F1:0x40 i = 0
62 * F1:0x48 i = 1
63 * F1:0x50 i = 2
64 * F1:0x58 i = 3
65 * F1:0x60 i = 4
66 * F1:0x68 i = 5
67 * F1:0x70 i = 6
68 * F1:0x78 i = 7
69 * [ 0: 0] Read Enable
70 * 0 = Reads Disabled
71 * 1 = Reads Enabled
72 * [ 1: 1] Write Enable
73 * 0 = Writes Disabled
74 * 1 = Writes Enabled
75 * [ 7: 2] Reserved
76 * [10: 8] Interleave Enable
77 * 000 = No interleave
78 * 001 = Interleave on A[12] (2 nodes)
79 * 010 = reserved
80 * 011 = Interleave on A[12] and A[14] (4 nodes)
81 * 100 = reserved
82 * 101 = reserved
83 * 110 = reserved
84 * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
85 * [15:11] Reserved
86 * [13:16] DRAM Base Address i Bits 39-24
87 * This field defines the upper address bits of a 40-bit address
88 * that define the start of the DRAM region.
89 */
90// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CONFIG_CAR_FAM10
91 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000,
92 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000,
93 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000,
94 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x60), 0x0000f8fc, 0x00000000,
95 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x68), 0x0000f8fc, 0x00000000,
96 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x70), 0x0000f8fc, 0x00000000,
97 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x78), 0x0000f8fc, 0x00000000,
98
99 /* Memory-Mapped I/O Limit i Registers
100 * F1:0x84 i = 0
101 * F1:0x8C i = 1
102 * F1:0x94 i = 2
103 * F1:0x9C i = 3
104 * F1:0xA4 i = 4
105 * F1:0xAC i = 5
106 * F1:0xB4 i = 6
107 * F1:0xBC i = 7
108 * [ 2: 0] Destination Node ID
109 * 000 = Node 0
110 * 001 = Node 1
111 * 010 = Node 2
112 * 011 = Node 3
113 * 100 = Node 4
114 * 101 = Node 5
115 * 110 = Node 6
116 * 111 = Node 7
117 * [ 3: 3] Reserved
118 * [ 5: 4] Destination Link ID
119 * 00 = Link 0
120 * 01 = Link 1
121 * 10 = Link 2
122 * 11 = Reserved
123 * [ 6: 6] Reserved
124 * [ 7: 7] Non-Posted
125 * 0 = CPU writes may be posted
126 * 1 = CPU writes must be non-posted
127 * [31: 8] Memory-Mapped I/O Limit Address i (39-16)
128 * This field defines the upp adddress bits of a 40-bit address that
129 * defines the end of a memory-mapped I/O region n
130 */
131 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000,
132 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000,
133 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x94), 0x00000048, 0x00000000,
134 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x9C), 0x00000048, 0x00000000,
135 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000,
136 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000,
137 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000,
138// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000048, 0x00ffff00,
139
140 /* Memory-Mapped I/O Base i Registers
141 * F1:0x80 i = 0
142 * F1:0x88 i = 1
143 * F1:0x90 i = 2
144 * F1:0x98 i = 3
145 * F1:0xA0 i = 4
146 * F1:0xA8 i = 5
147 * F1:0xB0 i = 6
148 * F1:0xB8 i = 7
149 * [ 0: 0] Read Enable
150 * 0 = Reads disabled
151 * 1 = Reads Enabled
152 * [ 1: 1] Write Enable
153 * 0 = Writes disabled
154 * 1 = Writes Enabled
155 * [ 2: 2] Cpu Disable
156 * 0 = Cpu can use this I/O range
157 * 1 = Cpu requests do not use this I/O range
158 * [ 3: 3] Lock
159 * 0 = base/limit registers i are read/write
160 * 1 = base/limit registers i are read-only
161 * [ 7: 4] Reserved
162 * [31: 8] Memory-Mapped I/O Base Address i (39-16)
163 * This field defines the upper address bits of a 40bit address
164 * that defines the start of memory-mapped I/O region i
165 */
166 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000,
167 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x88), 0x000000f0, 0x00000000,
168 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x90), 0x000000f0, 0x00000000,
169 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x98), 0x000000f0, 0x00000000,
170 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000,
171 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000,
172 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000,
173// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB8), 0x000000f0, 0x00fc0003,
174
175 /* PCI I/O Limit i Registers
176 * F1:0xC4 i = 0
177 * F1:0xCC i = 1
178 * F1:0xD4 i = 2
179 * F1:0xDC i = 3
180 * [ 2: 0] Destination Node ID
181 * 000 = Node 0
182 * 001 = Node 1
183 * 010 = Node 2
184 * 011 = Node 3
185 * 100 = Node 4
186 * 101 = Node 5
187 * 110 = Node 6
188 * 111 = Node 7
189 * [ 3: 3] Reserved
190 * [ 5: 4] Destination Link ID
191 * 00 = Link 0
192 * 01 = Link 1
193 * 10 = Link 2
194 * 11 = reserved
195 * [11: 6] Reserved
196 * [24:12] PCI I/O Limit Address i
197 * This field defines the end of PCI I/O region n
198 * [31:25] Reserved
199 */
200// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x01fff000,
201 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000,
202 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000,
203 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000,
204
205 /* PCI I/O Base i Registers
206 * F1:0xC0 i = 0
207 * F1:0xC8 i = 1
208 * F1:0xD0 i = 2
209 * F1:0xD8 i = 3
210 * [ 0: 0] Read Enable
211 * 0 = Reads Disabled
212 * 1 = Reads Enabled
213 * [ 1: 1] Write Enable
214 * 0 = Writes Disabled
215 * 1 = Writes Enabled
216 * [ 3: 2] Reserved
217 * [ 4: 4] VGA Enable
218 * 0 = VGA matches Disabled
219 * 1 = matches all address < 64K and where A[9:0] is in the
220 * range 3B0-3BB or 3C0-3DF independen of the base & limit registers
221 * [ 5: 5] ISA Enable
222 * 0 = ISA matches Disabled
223 * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
224 * from matching agains this base/limit pair
225 * [11: 6] Reserved
226 * [24:12] PCI I/O Base i
227 * This field defines the start of PCI I/O region n
228 * [31:25] Reserved
229 */
230// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00000003,
231 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000,
232 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000,
233 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000,
234
235 /* Config Base and Limit i Registers
236 * F1:0xE0 i = 0
237 * F1:0xE4 i = 1
238 * F1:0xE8 i = 2
239 * F1:0xEC i = 3
240 * [ 0: 0] Read Enable
241 * 0 = Reads Disabled
242 * 1 = Reads Enabled
243 * [ 1: 1] Write Enable
244 * 0 = Writes Disabled
245 * 1 = Writes Enabled
246 * [ 2: 2] Device Number Compare Enable
247 * 0 = The ranges are based on bus number
248 * 1 = The ranges are ranges of devices on bus 0
249 * [ 3: 3] Reserved
250 * [ 6: 4] Destination Node
251 * 000 = Node 0
252 * 001 = Node 1
253 * 010 = Node 2
254 * 011 = Node 3
255 * 100 = Node 4
256 * 101 = Node 5
257 * 110 = Node 6
258 * 111 = Node 7
259 * [ 7: 7] Reserved
260 * [ 9: 8] Destination Link
261 * 00 = Link 0
262 * 01 = Link 1
263 * 10 = Link 2
264 * 11 - Reserved
265 * [15:10] Reserved
266 * [23:16] Bus Number Base i
267 * This field defines the lowest bus number in configuration region i
268 * [31:24] Bus Number Limit i
269 * This field defines the highest bus number in configuration regin i
270 */
271// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0
272 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000,
273 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000,
274 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000,
275 };
276
277 int max;
278 max = ARRAY_SIZE(register_values);
279 setup_resource_map(register_values, max);
280}
281