Angel Pons | 7a400e2 | 2020-04-03 01:23:31 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Tristan Corrick | 44095c1 | 2018-12-22 00:04:18 +1300 | [diff] [blame] | 2 | |
Angel Pons | d37b7d8 | 2020-07-03 23:52:34 +0200 | [diff] [blame] | 3 | #include <stdint.h> |
Tristan Corrick | 44095c1 | 2018-12-22 00:04:18 +1300 | [diff] [blame] | 4 | #include <northbridge/intel/haswell/haswell.h> |
Angel Pons | 45f448f | 2020-07-03 14:46:47 +0200 | [diff] [blame] | 5 | #include <northbridge/intel/haswell/raminit.h> |
Tristan Corrick | 44095c1 | 2018-12-22 00:04:18 +1300 | [diff] [blame] | 6 | #include <southbridge/intel/lynxpoint/pch.h> |
Tristan Corrick | 44095c1 | 2018-12-22 00:04:18 +1300 | [diff] [blame] | 7 | |
Angel Pons | 6e1c471 | 2020-07-03 13:05:10 +0200 | [diff] [blame] | 8 | void mainboard_config_rcba(void) |
| 9 | { |
| 10 | RCBA16(D31IR) = DIR_ROUTE(PIRQA, PIRQD, PIRQC, PIRQA); |
| 11 | RCBA16(D29IR) = DIR_ROUTE(PIRQH, PIRQD, PIRQA, PIRQC); |
| 12 | RCBA16(D28IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD); |
| 13 | RCBA16(D27IR) = DIR_ROUTE(PIRQG, PIRQB, PIRQC, PIRQD); |
| 14 | RCBA16(D26IR) = DIR_ROUTE(PIRQA, PIRQF, PIRQC, PIRQD); |
| 15 | RCBA16(D25IR) = DIR_ROUTE(PIRQE, PIRQF, PIRQG, PIRQH); |
| 16 | RCBA16(D22IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD); |
| 17 | RCBA16(D20IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD); |
| 18 | } |
Tristan Corrick | 44095c1 | 2018-12-22 00:04:18 +1300 | [diff] [blame] | 19 | |
Angel Pons | d37b7d8 | 2020-07-03 23:52:34 +0200 | [diff] [blame] | 20 | void mb_get_spd_map(uint8_t spd_map[4]) |
| 21 | { |
| 22 | spd_map[0] = 0xa0; |
| 23 | spd_map[1] = 0xa2; |
| 24 | spd_map[2] = 0xa4; |
| 25 | spd_map[3] = 0xa6; |
| 26 | } |
| 27 | |
Angel Pons | a3c6ed0 | 2021-02-11 13:59:12 +0100 | [diff] [blame] | 28 | const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = { |
| 29 | /* Length, Enable, OCn#, Location */ |
| 30 | { 0x0040, 1, 0, USB_PORT_INTERNAL }, |
| 31 | { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, |
| 32 | { 0x0110, 1, 1, USB_PORT_BACK_PANEL }, |
| 33 | { 0x0110, 1, 1, USB_PORT_BACK_PANEL }, |
| 34 | { 0x0110, 1, 2, USB_PORT_BACK_PANEL }, |
| 35 | { 0x0110, 1, 2, USB_PORT_BACK_PANEL }, |
| 36 | { 0x0040, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP }, |
| 37 | { 0x0040, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP }, |
| 38 | { 0x0040, 1, 4, USB_PORT_BACK_PANEL }, |
| 39 | { 0x0040, 1, 4, USB_PORT_BACK_PANEL }, |
| 40 | { 0x0040, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP }, |
| 41 | { 0x0040, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP }, |
| 42 | { 0x0040, 1, 6, USB_PORT_BACK_PANEL }, |
| 43 | { 0x0040, 1, 6, USB_PORT_BACK_PANEL }, |
| 44 | }; |
Tristan Corrick | 44095c1 | 2018-12-22 00:04:18 +1300 | [diff] [blame] | 45 | |
Angel Pons | a3c6ed0 | 2021-02-11 13:59:12 +0100 | [diff] [blame] | 46 | const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = { |
| 47 | /* Enable, OCn# */ |
| 48 | { 1, 1 }, |
| 49 | { 1, 1 }, |
| 50 | { 0, USB_OC_PIN_SKIP }, |
| 51 | { 0, USB_OC_PIN_SKIP }, |
| 52 | { 1, 3 }, |
| 53 | { 1, 3 }, |
| 54 | }; |