Angel Pons | 7a400e2 | 2020-04-03 01:23:31 +0200 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | /* This file is part of the coreboot project. */ |
Tristan Corrick | 44095c1 | 2018-12-22 00:04:18 +1300 | [diff] [blame] | 3 | |
| 4 | #include <cpu/intel/haswell/haswell.h> |
Kyösti Mälkki | cd7a70f | 2019-08-17 20:51:08 +0300 | [diff] [blame] | 5 | #include <arch/romstage.h> |
Tristan Corrick | 44095c1 | 2018-12-22 00:04:18 +1300 | [diff] [blame] | 6 | #include <northbridge/intel/haswell/haswell.h> |
| 7 | #include <northbridge/intel/haswell/pei_data.h> |
| 8 | #include <southbridge/intel/common/gpio.h> |
| 9 | #include <southbridge/intel/lynxpoint/pch.h> |
| 10 | #include <stdint.h> |
Tristan Corrick | 44095c1 | 2018-12-22 00:04:18 +1300 | [diff] [blame] | 11 | |
| 12 | static const struct rcba_config_instruction rcba_config[] = { |
| 13 | RCBA_SET_REG_16(D31IR, DIR_ROUTE(PIRQA, PIRQD, PIRQC, PIRQA)), |
| 14 | RCBA_SET_REG_16(D29IR, DIR_ROUTE(PIRQH, PIRQD, PIRQA, PIRQC)), |
| 15 | RCBA_SET_REG_16(D28IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)), |
| 16 | RCBA_SET_REG_16(D27IR, DIR_ROUTE(PIRQG, PIRQB, PIRQC, PIRQD)), |
| 17 | RCBA_SET_REG_16(D26IR, DIR_ROUTE(PIRQA, PIRQF, PIRQC, PIRQD)), |
| 18 | RCBA_SET_REG_16(D25IR, DIR_ROUTE(PIRQE, PIRQF, PIRQG, PIRQH)), |
| 19 | RCBA_SET_REG_16(D22IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)), |
| 20 | RCBA_SET_REG_16(D20IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)), |
| 21 | |
| 22 | RCBA_RMW_REG_32(FD, ~0UL, PCH_DISABLE_ALWAYS), |
| 23 | |
| 24 | RCBA_END_CONFIG, |
| 25 | }; |
| 26 | |
Kyösti Mälkki | 157b189 | 2019-08-16 14:02:25 +0300 | [diff] [blame] | 27 | void mainboard_romstage_entry(void) |
Tristan Corrick | 44095c1 | 2018-12-22 00:04:18 +1300 | [diff] [blame] | 28 | { |
| 29 | struct pei_data pei_data = { |
| 30 | .pei_version = PEI_VERSION, |
| 31 | .mchbar = (uintptr_t)DEFAULT_MCHBAR, |
| 32 | .dmibar = (uintptr_t)DEFAULT_DMIBAR, |
| 33 | .epbar = DEFAULT_EPBAR, |
Kyösti Mälkki | 503d324 | 2019-03-05 07:54:28 +0200 | [diff] [blame] | 34 | .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, |
Tristan Corrick | 44095c1 | 2018-12-22 00:04:18 +1300 | [diff] [blame] | 35 | .smbusbar = SMBUS_IO_BASE, |
| 36 | .wdbbar = 0x4000000, |
| 37 | .wdbsize = 0x1000, |
| 38 | .hpet_address = HPET_ADDR, |
| 39 | .rcba = (uintptr_t)DEFAULT_RCBA, |
| 40 | .pmbase = DEFAULT_PMBASE, |
| 41 | .gpiobase = DEFAULT_GPIOBASE, |
| 42 | .temp_mmio_base = 0xfed08000, |
| 43 | .system_type = 1, /* desktop/server */ |
| 44 | .tseg_size = CONFIG_SMM_TSEG_SIZE, |
| 45 | .spd_addresses = { 0xa0, 0xa2, 0xa4, 0xa6 }, |
| 46 | .ec_present = 0, |
| 47 | .ddr_refresh_2x = 1, |
| 48 | .max_ddr3_freq = 1600, |
| 49 | .usb2_ports = { |
| 50 | /* Length, Enable, OCn#, Location */ |
| 51 | { 0x0040, 1, 0, USB_PORT_INTERNAL }, |
| 52 | { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, |
| 53 | { 0x0110, 1, 1, USB_PORT_BACK_PANEL }, |
| 54 | { 0x0110, 1, 1, USB_PORT_BACK_PANEL }, |
| 55 | { 0x0110, 1, 2, USB_PORT_BACK_PANEL }, |
| 56 | { 0x0110, 1, 2, USB_PORT_BACK_PANEL }, |
| 57 | { 0x0040, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP }, |
| 58 | { 0x0040, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP }, |
| 59 | { 0x0040, 1, 4, USB_PORT_BACK_PANEL }, |
| 60 | { 0x0040, 1, 4, USB_PORT_BACK_PANEL }, |
| 61 | { 0x0040, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP }, |
| 62 | { 0x0040, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP }, |
| 63 | { 0x0040, 1, 6, USB_PORT_BACK_PANEL }, |
| 64 | { 0x0040, 1, 6, USB_PORT_BACK_PANEL }, |
| 65 | }, |
| 66 | .usb3_ports = { |
| 67 | /* Enable, OCn# */ |
| 68 | { 1, 1 }, |
| 69 | { 1, 1 }, |
| 70 | { 0, USB_OC_PIN_SKIP }, |
| 71 | { 0, USB_OC_PIN_SKIP }, |
| 72 | { 1, 3 }, |
| 73 | { 1, 3 }, |
| 74 | }, |
| 75 | }; |
| 76 | |
| 77 | struct romstage_params romstage_params = { |
| 78 | .pei_data = &pei_data, |
| 79 | .gpio_map = &mainboard_gpio_map, |
| 80 | .rcba_config = rcba_config, |
Tristan Corrick | 44095c1 | 2018-12-22 00:04:18 +1300 | [diff] [blame] | 81 | }; |
| 82 | |
| 83 | romstage_common(&romstage_params); |
| 84 | } |