Lee Leahy | 3dad489 | 2015-05-05 11:14:02 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com> |
| 5 | * Copyright (C) 2007-2008 coresystems GmbH |
| 6 | * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. |
Lee Leahy | b5ad827 | 2015-04-20 15:29:16 -0700 | [diff] [blame] | 7 | * Copyright (C) 2015 Intel Corp. |
Lee Leahy | 3dad489 | 2015-05-05 11:14:02 -0700 | [diff] [blame] | 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU General Public License as published by |
| 11 | * the Free Software Foundation; version 2 of the License. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software |
Patrick Georgi | b890a12 | 2015-03-26 15:17:45 +0100 | [diff] [blame] | 20 | * Foundation, Inc. |
Lee Leahy | 3dad489 | 2015-05-05 11:14:02 -0700 | [diff] [blame] | 21 | */ |
| 22 | |
Lee Leahy | b5ad827 | 2015-04-20 15:29:16 -0700 | [diff] [blame] | 23 | /* |
| 24 | * Replacement for cache_as_ram.inc when using the FSP binary. This code |
| 25 | * locates the FSP binary, initializes the cache as RAM and performs the |
| 26 | * first stage of initialization. Next this code switches the stack from |
| 27 | * the cache to RAM and then disables the cache as RAM. Finally this code |
| 28 | * performs the final stage of initialization. |
| 29 | */ |
| 30 | |
Aaron Durbin | 909c512 | 2015-09-29 17:41:30 -0500 | [diff] [blame^] | 31 | #include <rules.h> |
Lee Leahy | 3dad489 | 2015-05-05 11:14:02 -0700 | [diff] [blame] | 32 | |
Lee Leahy | 3dad489 | 2015-05-05 11:14:02 -0700 | [diff] [blame] | 33 | #define LHLT_DELAY 0x50000 /* I/O delay between post codes on failure */ |
| 34 | |
Lee Leahy | b5ad827 | 2015-04-20 15:29:16 -0700 | [diff] [blame] | 35 | /* |
| 36 | * eax: BIST value |
| 37 | * mm0: low 32-bits of TSC value |
| 38 | * mm1: high 32-bits of TSC value |
| 39 | */ |
| 40 | |
| 41 | mov %eax, %edi |
Lee Leahy | 3dad489 | 2015-05-05 11:14:02 -0700 | [diff] [blame] | 42 | |
| 43 | cache_as_ram: |
| 44 | post_code(0x20) |
| 45 | |
| 46 | /* |
Lee Leahy | b5ad827 | 2015-04-20 15:29:16 -0700 | [diff] [blame] | 47 | * edi: BIST value |
| 48 | * mm0: low 32-bits of TSC value |
| 49 | * mm1: high 32-bits of TSC value |
| 50 | */ |
| 51 | |
| 52 | /* |
Lee Leahy | 3dad489 | 2015-05-05 11:14:02 -0700 | [diff] [blame] | 53 | * Find the FSP binary in cbfs. |
| 54 | * Make a fake stack that has the return value back to this code. |
| 55 | */ |
Lee Leahy | b5ad827 | 2015-04-20 15:29:16 -0700 | [diff] [blame] | 56 | lea fake_fsp_stack, %esp |
| 57 | jmp find_fsp |
Lee Leahy | 3dad489 | 2015-05-05 11:14:02 -0700 | [diff] [blame] | 58 | find_fsp_ret: |
| 59 | /* Save the FSP location */ |
Lee Leahy | b5ad827 | 2015-04-20 15:29:16 -0700 | [diff] [blame] | 60 | mov %eax, %ebp |
| 61 | |
| 62 | /* |
| 63 | * Only when a valid FSP binary is found at CONFIG_FSP_LOC is |
| 64 | * the returned FSP_INFO_HEADER structure address above the base |
| 65 | * address of FSP binary specified by the CONFIG_FSP_LOC value. |
| 66 | * All of the error values are in the 0x8xxxxxxx range which are |
| 67 | * below the CONFIG_FSP_LOC value. |
| 68 | */ |
| 69 | cmp $CONFIG_FSP_LOC, %eax |
| 70 | jbe halt1 |
Lee Leahy | 3dad489 | 2015-05-05 11:14:02 -0700 | [diff] [blame] | 71 | |
| 72 | post_code(0x22) |
| 73 | |
| 74 | /* Calculate entry into FSP */ |
Lee Leahy | b5ad827 | 2015-04-20 15:29:16 -0700 | [diff] [blame] | 75 | mov 0x30(%ebp), %eax /* Load TempRamInitEntry */ |
| 76 | add 0x1c(%ebp), %eax /* add in the offset for FSP */ |
Lee Leahy | 3dad489 | 2015-05-05 11:14:02 -0700 | [diff] [blame] | 77 | |
| 78 | /* |
| 79 | * Pass early init variables on a fake stack (no memory yet) |
| 80 | * as well as the return location |
| 81 | */ |
Lee Leahy | b5ad827 | 2015-04-20 15:29:16 -0700 | [diff] [blame] | 82 | lea CAR_init_stack, %esp |
Lee Leahy | 3dad489 | 2015-05-05 11:14:02 -0700 | [diff] [blame] | 83 | |
| 84 | /* |
Lee Leahy | b5ad827 | 2015-04-20 15:29:16 -0700 | [diff] [blame] | 85 | * BIST value is zero |
| 86 | * eax: TempRamInitApi address |
| 87 | * ebp: FSP_INFO_HEADER address |
| 88 | * edi: BIST value |
| 89 | * esi: Not used |
| 90 | * mm0: low 32-bits of TSC value |
| 91 | * mm1: high 32-bits of TSC value |
Lee Leahy | 3dad489 | 2015-05-05 11:14:02 -0700 | [diff] [blame] | 92 | */ |
Lee Leahy | 3dad489 | 2015-05-05 11:14:02 -0700 | [diff] [blame] | 93 | |
Lee Leahy | b5ad827 | 2015-04-20 15:29:16 -0700 | [diff] [blame] | 94 | /* call FSP binary to setup temporary stack */ |
| 95 | jmp *%eax |
| 96 | |
| 97 | CAR_init_done: |
| 98 | addl $4, %esp |
| 99 | |
| 100 | /* |
| 101 | * ebp: FSP_INFO_HEADER address |
| 102 | * ecx: Temp RAM base |
| 103 | * edx: Temp RAM top |
| 104 | * edi: BIST value |
| 105 | * mm0: low 32-bits of TSC value |
| 106 | * mm1: high 32-bits of TSC value |
| 107 | */ |
| 108 | |
| 109 | cmp $0, %eax |
| 110 | jne halt2 |
| 111 | |
| 112 | /* Setup bootloader stack */ |
| 113 | movl %edx, %esp |
| 114 | |
Lee Leahy | b5ad827 | 2015-04-20 15:29:16 -0700 | [diff] [blame] | 115 | /* |
| 116 | * ebp: FSP_INFO_HEADER address |
| 117 | * ecx: Temp RAM base |
| 118 | * edx: Temp RAM top |
Aaron Durbin | e1ecfc9 | 2015-09-16 15:18:04 -0500 | [diff] [blame] | 119 | * edi: BIST value |
Lee Leahy | b5ad827 | 2015-04-20 15:29:16 -0700 | [diff] [blame] | 120 | * esp: Top of stack in temp RAM |
| 121 | * mm0: low 32-bits of TSC value |
| 122 | * mm1: high 32-bits of TSC value |
Lee Leahy | b5ad827 | 2015-04-20 15:29:16 -0700 | [diff] [blame] | 123 | */ |
| 124 | |
Aaron Durbin | e6af4be | 2015-09-24 12:26:31 -0500 | [diff] [blame] | 125 | /* Create cache_as_ram_params on stack */ |
Aaron Durbin | e1ecfc9 | 2015-09-16 15:18:04 -0500 | [diff] [blame] | 126 | pushl %edx /* bootloader CAR end */ |
| 127 | pushl %ecx /* bootloader CAR begin */ |
| 128 | pushl %ebp /* FSP_INFO_HEADER */ |
Aaron Durbin | e1ecfc9 | 2015-09-16 15:18:04 -0500 | [diff] [blame] | 129 | pushl %edi /* bist */ |
| 130 | movd %mm1, %eax |
| 131 | pushl %eax /* tsc[63:32] */ |
| 132 | movd %mm0, %eax |
| 133 | pushl %eax /* tsc[31:0] */ |
| 134 | pushl %esp /* pointer to cache_as_ram_params */ |
| 135 | |
| 136 | /* Save FSP_INFO_HEADER location in ebx */ |
| 137 | mov %ebp, %ebx |
| 138 | |
Lee Leahy | b5ad827 | 2015-04-20 15:29:16 -0700 | [diff] [blame] | 139 | /* Coreboot assumes stack/heap region will be zero */ |
| 140 | cld |
| 141 | movl %ecx, %edi |
| 142 | neg %ecx |
Aaron Durbin | e1ecfc9 | 2015-09-16 15:18:04 -0500 | [diff] [blame] | 143 | /* Only clear up to current stack value. */ |
| 144 | add %esp, %ecx |
Lee Leahy | b5ad827 | 2015-04-20 15:29:16 -0700 | [diff] [blame] | 145 | shrl $2, %ecx |
| 146 | xorl %eax, %eax |
| 147 | rep stosl |
| 148 | |
Lee Leahy | 3dad489 | 2015-05-05 11:14:02 -0700 | [diff] [blame] | 149 | before_romstage: |
| 150 | post_code(0x23) |
| 151 | |
Aaron Durbin | e6af4be | 2015-09-24 12:26:31 -0500 | [diff] [blame] | 152 | /* Call cache_as_ram_main(struct cache_as_ram_params *) */ |
| 153 | call cache_as_ram_main |
Lee Leahy | 3dad489 | 2015-05-05 11:14:02 -0700 | [diff] [blame] | 154 | |
Aaron Durbin | 909c512 | 2015-09-29 17:41:30 -0500 | [diff] [blame^] | 155 | /* One will never return from cache_as_ram_main() in verstage so there's |
| 156 | * no such thing as after ram init. */ |
| 157 | #if !ENV_VERSTAGE |
Aaron Durbin | e6af4be | 2015-09-24 12:26:31 -0500 | [diff] [blame] | 158 | #include "after_raminit.S" |
Aaron Durbin | 909c512 | 2015-09-29 17:41:30 -0500 | [diff] [blame^] | 159 | #endif |
Lee Leahy | b5ad827 | 2015-04-20 15:29:16 -0700 | [diff] [blame] | 160 | |
| 161 | movb $0x69, %ah |
| 162 | jmp .Lhlt |
Lee Leahy | 3dad489 | 2015-05-05 11:14:02 -0700 | [diff] [blame] | 163 | |
| 164 | halt1: |
| 165 | /* |
Lee Leahy | b5ad827 | 2015-04-20 15:29:16 -0700 | [diff] [blame] | 166 | * Failures for postcode 0xBA - failed in fsp_fih_early_find() |
Lee Leahy | 3dad489 | 2015-05-05 11:14:02 -0700 | [diff] [blame] | 167 | * |
| 168 | * Values are: |
| 169 | * 0x01 - FV signature, "_FVH" not present |
| 170 | * 0x02 - FFS GUID not present |
| 171 | * 0x03 - FSP INFO Header not found |
| 172 | * 0x04 - ImageBase does not equal CONFIG_FSP_LOC - Is the FSP rebased to |
| 173 | * a different location, or does it need to be? |
| 174 | * 0x05 - FSP INFO Header signature "FSPH" not found |
| 175 | * 0x06 - FSP Image ID is not the expected ID. |
| 176 | */ |
Lee Leahy | b5ad827 | 2015-04-20 15:29:16 -0700 | [diff] [blame] | 177 | movb $0xBA, %ah |
| 178 | jmp .Lhlt |
Lee Leahy | 3dad489 | 2015-05-05 11:14:02 -0700 | [diff] [blame] | 179 | |
| 180 | halt2: |
| 181 | /* |
| 182 | * Failures for postcode 0xBB - failed in the FSP: |
| 183 | * |
| 184 | * 0x00 - FSP_SUCCESS: Temp RAM was initialized successfully. |
| 185 | * 0x02 - FSP_INVALID_PARAMETER: Input parameters are invalid. |
Lee Leahy | 3dad489 | 2015-05-05 11:14:02 -0700 | [diff] [blame] | 186 | * 0x03 - FSP_UNSUPPORTED: The FSP calling conditions were not met. |
| 187 | * 0x07 - FSP_DEVICE_ERROR: Temp RAM initialization failed |
Lee Leahy | b5ad827 | 2015-04-20 15:29:16 -0700 | [diff] [blame] | 188 | * 0x0E - FSP_NOT_FOUND: No valid microcode was found in the microcode region. |
Lee Leahy | 3dad489 | 2015-05-05 11:14:02 -0700 | [diff] [blame] | 189 | * 0x14 - FSP_ALREADY_STARTED: Temp RAM initialization has been invoked |
| 190 | */ |
Lee Leahy | b5ad827 | 2015-04-20 15:29:16 -0700 | [diff] [blame] | 191 | movb $0xBB, %ah |
| 192 | jmp .Lhlt |
| 193 | |
Lee Leahy | 3dad489 | 2015-05-05 11:14:02 -0700 | [diff] [blame] | 194 | .Lhlt: |
Lee Leahy | b5ad827 | 2015-04-20 15:29:16 -0700 | [diff] [blame] | 195 | xchg %al, %ah |
| 196 | #if IS_ENABLED(CONFIG_POST_IO) |
| 197 | outb %al, $CONFIG_POST_IO_PORT |
Lee Leahy | 3dad489 | 2015-05-05 11:14:02 -0700 | [diff] [blame] | 198 | #else |
| 199 | post_code(POST_DEAD_CODE) |
| 200 | #endif |
Lee Leahy | b5ad827 | 2015-04-20 15:29:16 -0700 | [diff] [blame] | 201 | movl $LHLT_DELAY, %ecx |
Lee Leahy | 3dad489 | 2015-05-05 11:14:02 -0700 | [diff] [blame] | 202 | .Lhlt_Delay: |
Lee Leahy | b5ad827 | 2015-04-20 15:29:16 -0700 | [diff] [blame] | 203 | outb %al, $0xED |
| 204 | loop .Lhlt_Delay |
| 205 | jmp .Lhlt |
Lee Leahy | 3dad489 | 2015-05-05 11:14:02 -0700 | [diff] [blame] | 206 | |
| 207 | /* |
| 208 | * esp is set to this location so that the call into and return from the FSP |
| 209 | * in find_fsp will work. |
| 210 | */ |
| 211 | .align 4 |
| 212 | fake_fsp_stack: |
Lee Leahy | b5ad827 | 2015-04-20 15:29:16 -0700 | [diff] [blame] | 213 | .long find_fsp_ret |
Lee Leahy | a887492 | 2015-08-26 14:58:29 -0700 | [diff] [blame] | 214 | .long CONFIG_FSP_LOC /* FSP base address */ |
Lee Leahy | 3dad489 | 2015-05-05 11:14:02 -0700 | [diff] [blame] | 215 | |
| 216 | CAR_init_params: |
Lee Leahy | b5ad827 | 2015-04-20 15:29:16 -0700 | [diff] [blame] | 217 | .long CONFIG_CPU_MICROCODE_CBFS_LOC /* Microcode Location */ |
| 218 | .long CONFIG_CPU_MICROCODE_CBFS_LEN /* Microcode Length */ |
| 219 | .long 0xFFFFFFFF - CONFIG_CBFS_SIZE + 1 /* Firmware Location */ |
| 220 | .long CONFIG_CBFS_SIZE /* Total Firmware Length */ |
Lee Leahy | 3dad489 | 2015-05-05 11:14:02 -0700 | [diff] [blame] | 221 | |
| 222 | CAR_init_stack: |
Lee Leahy | b5ad827 | 2015-04-20 15:29:16 -0700 | [diff] [blame] | 223 | .long CAR_init_done |
| 224 | .long CAR_init_params |