Vladimir Serbinenko | fa1d688 | 2014-10-19 02:50:45 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2010 coresystems GmbH |
| 5 | * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. |
| 6 | * Copyright (C) 2014 Vladimir Serbinenko |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; version 2 of the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
Vladimir Serbinenko | fa1d688 | 2014-10-19 02:50:45 +0200 | [diff] [blame] | 16 | */ |
| 17 | |
| 18 | #include <stdint.h> |
Vladimir Serbinenko | fa1d688 | 2014-10-19 02:50:45 +0200 | [diff] [blame] | 19 | #include <console/console.h> |
| 20 | #include <arch/io.h> |
Elyes HAOUAS | 1bc7b6e | 2019-05-05 16:29:41 +0200 | [diff] [blame] | 21 | #include <cf9_reset.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 22 | #include <device/pci_ops.h> |
Vladimir Serbinenko | fa1d688 | 2014-10-19 02:50:45 +0200 | [diff] [blame] | 23 | #include <cpu/x86/lapic.h> |
| 24 | #include <timestamp.h> |
| 25 | #include "sandybridge.h" |
| 26 | #include <cpu/x86/bist.h> |
| 27 | #include <cpu/intel/romstage.h> |
Alexandru Gagniuc | 8b2c8f1 | 2015-02-17 04:31:01 -0600 | [diff] [blame] | 28 | #include <device/pci_def.h> |
| 29 | #include <device/device.h> |
Alexandru Gagniuc | 8b2c8f1 | 2015-02-17 04:31:01 -0600 | [diff] [blame] | 30 | #include <northbridge/intel/sandybridge/chip.h> |
Elyes HAOUAS | 21b71ce6 | 2018-06-16 18:43:52 +0200 | [diff] [blame] | 31 | #include <southbridge/intel/bd82x6x/pch.h> |
Patrick Rudolph | e2f0a5f | 2019-03-24 14:47:47 +0100 | [diff] [blame] | 32 | #include <southbridge/intel/common/pmclib.h> |
Vladimir Serbinenko | fa1d688 | 2014-10-19 02:50:45 +0200 | [diff] [blame] | 33 | |
Patrick Rudolph | 45d4b17 | 2019-03-24 12:27:31 +0100 | [diff] [blame] | 34 | static void early_pch_reset_pmcon(void) |
Alexandru Gagniuc | 8b2c8f1 | 2015-02-17 04:31:01 -0600 | [diff] [blame] | 35 | { |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 36 | u8 reg8; |
Alexandru Gagniuc | 8b2c8f1 | 2015-02-17 04:31:01 -0600 | [diff] [blame] | 37 | |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 38 | // reset rtc power status |
Patrick Rudolph | 5c31af8 | 2017-05-03 17:47:54 +0200 | [diff] [blame] | 39 | reg8 = pci_read_config8(PCH_LPC_DEV, GEN_PMCON_3); |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 40 | reg8 &= ~(1 << 2); |
Patrick Rudolph | 5c31af8 | 2017-05-03 17:47:54 +0200 | [diff] [blame] | 41 | pci_write_config8(PCH_LPC_DEV, GEN_PMCON_3, reg8); |
Alexandru Gagniuc | 8b2c8f1 | 2015-02-17 04:31:01 -0600 | [diff] [blame] | 42 | } |
| 43 | |
Kyösti Mälkki | 75d139b | 2016-06-17 10:00:28 +0300 | [diff] [blame] | 44 | /* Platform has no romstage entry point under mainboard directory, |
| 45 | * so this one is named with prefix mainboard. |
| 46 | */ |
| 47 | void mainboard_romstage_entry(unsigned long bist) |
Vladimir Serbinenko | fa1d688 | 2014-10-19 02:50:45 +0200 | [diff] [blame] | 48 | { |
| 49 | int s3resume = 0; |
Vladimir Serbinenko | fa1d688 | 2014-10-19 02:50:45 +0200 | [diff] [blame] | 50 | |
Elyes HAOUAS | 1bc7b6e | 2019-05-05 16:29:41 +0200 | [diff] [blame] | 51 | if (MCHBAR16(SSKPD) == 0xCAFE) |
| 52 | system_reset(); |
Vladimir Serbinenko | fa1d688 | 2014-10-19 02:50:45 +0200 | [diff] [blame] | 53 | |
Vladimir Serbinenko | fa1d688 | 2014-10-19 02:50:45 +0200 | [diff] [blame] | 54 | if (bist == 0) |
| 55 | enable_lapic(); |
| 56 | |
Patrick Rudolph | 45d4b17 | 2019-03-24 12:27:31 +0100 | [diff] [blame] | 57 | /* Init LPC, GPIO, BARs, disable watchdog ... */ |
| 58 | early_pch_init(); |
Vladimir Serbinenko | fa1d688 | 2014-10-19 02:50:45 +0200 | [diff] [blame] | 59 | |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 60 | /* Initialize superio */ |
| 61 | mainboard_config_superio(); |
| 62 | |
Martin Roth | 128c104 | 2016-11-18 09:29:03 -0700 | [diff] [blame] | 63 | /* USB is initialized in MRC if MRC is used. */ |
Julius Werner | 5d1f9a0 | 2019-03-07 17:07:26 -0800 | [diff] [blame] | 64 | if (CONFIG(USE_NATIVE_RAMINIT)) { |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 65 | early_usb_init(mainboard_usb_ports); |
| 66 | } |
Vladimir Serbinenko | fa1d688 | 2014-10-19 02:50:45 +0200 | [diff] [blame] | 67 | |
| 68 | /* Initialize console device(s) */ |
| 69 | console_init(); |
| 70 | |
| 71 | /* Halt if there was a built in self test failure */ |
| 72 | report_bist_failure(bist); |
| 73 | |
| 74 | /* Perform some early chipset initialization required |
| 75 | * before RAM initialization can work |
| 76 | */ |
Patrick Rudolph | 74203de | 2017-11-20 11:57:01 +0100 | [diff] [blame] | 77 | sandybridge_early_initialization(); |
Vladimir Serbinenko | fa1d688 | 2014-10-19 02:50:45 +0200 | [diff] [blame] | 78 | printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n"); |
| 79 | |
| 80 | s3resume = southbridge_detect_s3_resume(); |
| 81 | |
| 82 | post_code(0x38); |
Vladimir Serbinenko | 609bd94 | 2016-01-31 14:00:54 +0100 | [diff] [blame] | 83 | |
| 84 | mainboard_early_init(s3resume); |
| 85 | |
Vladimir Serbinenko | fa1d688 | 2014-10-19 02:50:45 +0200 | [diff] [blame] | 86 | /* Enable SPD ROMs and DDR-III DRAM */ |
| 87 | enable_smbus(); |
| 88 | |
| 89 | post_code(0x39); |
| 90 | |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 91 | perform_raminit(s3resume); |
Vladimir Serbinenko | fa1d688 | 2014-10-19 02:50:45 +0200 | [diff] [blame] | 92 | |
| 93 | timestamp_add_now(TS_AFTER_INITRAM); |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 94 | |
| 95 | post_code(0x3b); |
| 96 | /* Perform some initialization that must run before stage2 */ |
Patrick Rudolph | 45d4b17 | 2019-03-24 12:27:31 +0100 | [diff] [blame] | 97 | early_pch_reset_pmcon(); |
Vladimir Serbinenko | fa1d688 | 2014-10-19 02:50:45 +0200 | [diff] [blame] | 98 | post_code(0x3c); |
| 99 | |
Vladimir Serbinenko | 33b535f | 2014-10-19 10:13:14 +0200 | [diff] [blame] | 100 | southbridge_configure_default_intmap(); |
Nico Huber | ff4025c | 2018-01-14 12:34:43 +0100 | [diff] [blame] | 101 | southbridge_rcba_config(); |
| 102 | mainboard_rcba_config(); |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 103 | |
Vladimir Serbinenko | fa1d688 | 2014-10-19 02:50:45 +0200 | [diff] [blame] | 104 | post_code(0x3d); |
| 105 | |
| 106 | northbridge_romstage_finalize(s3resume); |
| 107 | |
Vladimir Serbinenko | fa1d688 | 2014-10-19 02:50:45 +0200 | [diff] [blame] | 108 | post_code(0x3f); |
Vladimir Serbinenko | fa1d688 | 2014-10-19 02:50:45 +0200 | [diff] [blame] | 109 | } |